Port switching circuit, controller, solid state disk, storage product and server

Abstract

The invention relates to the technical field of solid state disks, and discloses a port switching circuit, a controller, a solid state disk, a storage product and a server, the port switching circuit comprises a mode recognition circuit and a gating circuit, when the mode recognition circuit recognizes that a plurality of external devices are connected, the mode recognition circuit outputs a multi-port signal to the gating circuit, and when the mode recognition circuit outputs the multi-port signal to the storage product; the multi-port signal is used for controlling the gating circuit to transmit control signals and data between one external device and one corresponding storage device. According to the access number of the external devices, the bus interfaces connected with the gating circuit are determined, that is, when one external device is accessed, only one bus interface is used, and the storage device is in a single-port mode, and when a plurality of external devices are accessed, each external device uses one bus interface, and the storage device is in a multi-port mode. Therefore, the single-port / multi-port SSD design is realized on a set of hardware single board, and the product specification of the multi-port SSD is made up.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state hard disks, and in particular to a port switching circuit, a controller, a solid state hard disk, a storage product and a server. Background Art

[0002] Solid State Disk (SSD), also known as solid-state drive, is a hard disk made of solid-state electronic storage chip arrays. Compared with mechanical hard disks (HDD), SSD has great advantages in speed, power consumption, capacity, noise, reliability and other performance. SSD includes SCSI SSD, SATA SSD, PCIe SSD, among which PCIe SSD has great advantages in bandwidth, latency and other performance, so PCIe SSD market share is increasing.

[0003] PCIe SSD is generally used in server products and storage products. PCIe SSD works in single-port mode in server products and in dual-port mode in storage products. However, when designing the main control of the SSD controller, due to factors such as the area within the chip die and product cost, the SSD main controller cannot support the dual-port working mode. At this time, hardware developers need to flexibly use peripheral hardware circuits and designs to implement the dual-port working mode of the SSD main controller, thereby realizing the product design of the dual-port SSD. Summary of the invention

[0004] In view of this, the present invention provides a port switching circuit, a controller, a solid state drive, a storage product and a server to solve the problem of how to realize that the SSD can support a single port and dual ports at the same time.

[0005] In the first aspect, the present invention provides a port switching circuit, which is used to realize signal and data transmission between an external device and a storage device. The port switching circuit includes: a mode recognition circuit and a gating circuit, wherein the first end of the mode recognition circuit is connected to the bus interface of the external device, and the second end of the mode recognition circuit is connected to the first end of the gating circuit; the second end of the gating circuit is connected to each bus interface of the storage device; when the mode recognition circuit recognizes that only one external device is connected, the mode recognition circuit outputs a single-port signal to the gating circuit, and the single-port signal is used to control the gating circuit to send the control signal sent by the external device to each bus interface, and control the gating circuit to realize the data transmission connection between the external device and any one or specified bus interface; when the mode recognition circuit recognizes that multiple external devices are connected, the mode recognition circuit outputs a multi-port signal to the gating circuit, and the multi-port signal is used to control the gating circuit to transmit the control signal and data between an external device and a corresponding bus interface.

[0006] The present invention determines the bus interface to which the selection circuit is connected according to the number of external devices connected, that is, when one external device is connected, only one bus interface is used, and the storage device is in a single-port mode; when multiple external devices are connected, each external device uses a bus interface, and the storage device is in a multi-port mode, thereby realizing a single-port / multi-port SSD design on a set of hardware boards, making up for the product specifications of the multi-port SSD, and improving the comprehensive competitiveness of the SSD products.

[0007] In an optional embodiment, the control signal includes: a reset signal and a clock signal, wherein the selection circuit sends the reset signal and clock signal sent by the external device to each bus interface based on the single-port signal, and each bus interface multiplexes the reset signal and the clock signal; the selection circuit sends the reset signal and the clock signal sent by each external device to a corresponding bus interface based on the multi-port signal.

[0008] In an optional embodiment, the storage device is a controller of a solid-state hard disk, and the controller of the solid-state hard disk includes a first bus interface and a second bus interface, the first bus interface includes 4 data interfaces, a clock signal interface, and a reset signal interface, and the second bus interface includes 2 data interfaces, a clock signal interface, and a reset signal interface, and the pattern recognition circuit includes: a U.2 interface connector, wherein the U.2 interface connector includes a first clock signal interface, a second clock signal interface, a first reset signal interface, a second reset signal interface, an enable output interface, and 4 data interfaces; the first end of the first clock signal interface and the first end of the first reset signal interface are respectively connected to the clock signal interface and the reset clock signal interface of the first external device, and the second end of the first clock signal interface and the second end of the first reset signal interface are connected to the first end of the gating circuit; the first end of the second clock signal interface and the first end of the second reset signal interface are respectively used to connect to the clock signal interface and the reset clock signal interface of the second external device, and the second end of the second clock signal interface and the second end of the second reset signal interface are connected to the first end of the gating circuit.

[0009] The present invention utilizes the single / dual port SSD identification signal of the U.2 interface to identify the number of peripheral devices so as to realize single-port and multi-port switching control.

[0010] In an optional embodiment, the selection circuit includes: a signal line switching circuit and a data line switching circuit, wherein the first end of the signal line switching circuit is connected to each clock signal interface, each reset signal interface, and enable output interface of the U.2 interface connector, and the second end of the signal line switching circuit is connected to each bus interface; the signal line switching circuit sends the clock signal and the reset signal to each bus interface based on a single-port signal; the signal line switching circuit transmits the clock signal and the reset signal sent by the first external device to the first bus interface, and transmits the clock signal and the reset signal sent by the second external device to the second bus interface based on a multi-port signal; the first end of the data line switching circuit is connected to each data interface and the enable output interface of the U.2 interface connector, and the second end of the data line switching circuit is connected to each data interface of each bus interface; when a single-port signal is received, the data line switching circuit realizes data transmission between the external device and the first bus interface; when a multi-port signal is received, the data line switching circuit realizes data transmission between the first external device and the first bus interface, and data transmission between the second external device and the second bus interface.

[0011] In an optional embodiment, the signal line switching circuit includes: a clock signal switching circuit and a reset signal switching circuit, wherein a first end of the clock signal switching circuit is connected to each clock signal interface of the U.2 interface connector, a second end of the clock signal switching circuit is connected to an enable output end of the U.2 interface connector, and a third end of the clock signal switching circuit is connected to a clock signal interface of each bus interface; when a single-port signal is received, the clock signal switching circuit transmits the clock signal to each bus interface; when a multi-port signal is received, the clock signal switching circuit transmits the clock signal of the first external device to the first bus interface and transmits the clock signal of the second external device to the second bus interface; a first end of the reset signal switching circuit is connected to each reset signal interface of the U.2 interface connector, a second end of the reset signal switching circuit is connected to the enable output end of the U.2 interface connector, and a third end of the reset signal switching circuit is connected to a reset signal interface of each bus interface; when a single-port signal is received, the reset signal switching circuit transmits the reset signal to each bus interface; when a multi-port signal is received, the reset signal switching circuit transmits the reset signal of the first external device to the first bus interface and transmits the reset signal of the second external device to the second bus interface.

[0012] In an optional embodiment, the clock signal switching circuit includes: 1 clock buffer and 1 2-to-1 clock signal multiplexer, wherein the first end of the clock buffer is connected to the first clock signal interface of the U.2 interface connector, and the second end of the clock buffer is connected to the third end of the 2-to-1 clock signal multiplexer; the first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

[0013] In an optional embodiment, the clock signal switching circuit includes: 1 signal direct line and 1 2-to-1 clock signal multiplexer, wherein the first end of the signal direct line is connected to the first clock signal interface of the U.2 interface connector, and the second end of the signal direct line is connected to the third end of the 2-to-1 clock signal multiplexer and the clock signal interface of the first bus interface; the first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

[0014] In an optional embodiment, the clock signal switching circuit includes: a first clock buffer, a second clock buffer, a first 2-to-1 clock multiplexer, and a second 2-to-1 clock multiplexer, wherein the first end of the first clock buffer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first clock buffer is connected to the clock signal interface of the first bus interface, and the second end of the first clock buffer is connected to the third end of the second 2-to-1 clock multiplexer; the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer The fourth end of the second clock buffer is connected to the clock signal interface of the first bus interface; the first end of the second clock buffer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second clock buffer is connected to the clock signal interface of the second bus interface, and the second end of the second clock buffer is connected to the third end of the first 2-to-1 clock multiplexer; the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface; when the clock signal interface of the external device is connected to the U.2 interface connector The first clock signal interface of the U.2 interface connector is connected to the first clock signal interface of the U.2 interface connector, when the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first clock buffer outputs a homologous clock signal to the first bus interface and the second 2-to-1 clock multiplexer, the second 2-to-1 clock multiplexer outputs the homologous clock signal to the second bus interface, and the first 2-to-1 clock multiplexer is locked; when the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector, when the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the second clock buffer outputs a homologous clock signal to the second bus interface and the first 2-to-1 clock multiplexer, the first 2 The select-1 clock multiplexer outputs the homologous clock signal to the first bus interface, and the second 2-to-1 clock multiplexer is locked; when the clock signal interface of the first external device and the clock signal interface of the second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive multi-port signals, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer are locked, and the first clock buffer outputs the homologous clock signal of the clock signal of the first external device to the first bus interface, and the second clock buffer outputs the homologous clock signal of the clock signal of the second external device to the second bus interface.

[0015] In an optional embodiment, the clock signal switching circuit includes: a first 2-to-1 clock multiplexer and a second 2-to-1 clock multiplexer, wherein the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the first 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, and the fourth end of the first 2-to-1 clock multiplexer is connected to the clock signal interface of the first bus interface; the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the second 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface; when the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector, the first 2-to-1 When the clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; when the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; when the clock signal interface of the first external device and the clock signal interface of the second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface, when the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the first external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the second external device to the second bus interface.

[0016] In an optional embodiment, the reset signal switching circuit includes: 1 signal direct line and 1 reset signal multiplexer, wherein the first end of the signal direct line is connected to the first reset signal interface of the U.2 interface connector, and the second end of the signal direct line is connected to the reset signal interface of the first bus interface; the first end of the reset signal multiplexer is connected to the second reset signal interface of the U.2 interface connector, the second end of the reset signal multiplexer is connected to the first end of the signal direct line, the third end of the reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the reset signal multiplexer is connected to the reset signal interface of the second bus interface.

[0017] In an optional embodiment, the reset signal switching circuit includes: a first reset signal multiplexer and a reset signal multiplexer, wherein the first end and the second end of the first reset signal multiplexer are connected to the first reset signal interface and the second reset signal interface of the U.2 interface connector, the third end of the first reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first reset signal multiplexer is connected to the reset signal interface of the first bus interface; the first end and the second end of the second reset signal multiplexer are connected to the second reset signal interface and the first reset signal interface of the U.2 interface connector, the third end of the second reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second reset signal multiplexer is connected to the reset signal interface of the second bus interface; when the reset signal interface of the external device is connected to the first reset signal interface of the U.2 interface connector, the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal , the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface; when the reset signal interface of the external device is connected to the second reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface; when the reset signal interface of the first external device and the reset signal interface of the second external device are respectively connected to the first reset signal interface and the second reset signal interface connected to the U.2 interface, and the first reset signal multiplexer and the second reset signal multiplexer receive a multi-port signal, the first reset signal multiplexer outputs the reset signal of the first external device to the first bus interface, and the second reset signal multiplexer outputs the reset signal of the second external device to the second bus interface.

[0018] In an optional embodiment, the data line switching circuit includes: a first data pass-through line, a second data pass-through line, a first data line switching subcircuit, and a second data line switching subcircuit, wherein the first data pass-through line connects the first data interface of the U.2 interface connector to the first data interface of the first bus interface; the second data pass-through line connects the second data interface of the U.2 interface connector to the second data interface of the first bus interface; the first end of the first data line switching subcircuit is connected to the third data interface of the U.2 interface connector, the second end of the first data line switching subcircuit is connected to the enable output port of the U.2 interface connector, and the third end of the first data line switching subcircuit is connected to the third data interface of the first bus interface and the first data interface of the second bus interface; the first end of the second data line switching subcircuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second data line switching subcircuit is connected to the enable output port of the U.2 interface connector, and the third end of the second data line switching subcircuit is connected to the fourth data interface of the first bus interface and the second data interface of the second bus interface.

[0019] In an optional embodiment, the first data line switching sub-circuit includes: a first sending switching circuit and a first receiving switching circuit, wherein the first end of the first sending switching circuit is connected to the third data interface of the first bus interface, the second end of the first sending switching circuit is connected to the first data interface of the second bus interface, the third end of the first sending switching circuit is connected to the third data interface of the U.2 interface connector, and the fourth end of the first sending switching circuit is connected to the enable output port of the U.2 interface connector; the first end of the first receiving switching circuit is connected to the third data interface of the U.2 interface connector, the second end of the first receiving switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the first receiving switching circuit is connected to the third data interface of the first bus interface, and the fourth end of the first receiving switching circuit is connected to the first data interface of the second bus interface.

[0020] In an optional embodiment, the second data line switching sub-circuit includes: a second sending switching circuit and a second receiving switching circuit, wherein the first end of the second sending switching circuit is connected to the fourth data interface of the first bus interface, the second end of the second sending switching circuit is connected to the second data interface of the second bus interface, the third end of the second sending switching circuit is connected to the fourth data interface of the U.2 interface connector, and the fourth end of the second sending switching circuit is connected to the enable output port of the U.2 interface connector; the first end of the second receiving switching circuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second receiving switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the second receiving switching circuit is connected to the fourth data interface of the first bus interface, and the second receiving switch The fourth end of the switching circuit is connected to the second data interface of the second bus interface; when the second sending switching circuit receives a single-port signal, the second sending switching circuit connects the fourth data interface of the first bus interface to the fourth data interface of the U.2 interface connector; when the second sending switching circuit receives a multi-port signal, the second sending switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector; when the second receiving switching circuit receives a single-port signal, the second receiving switching circuit connects the fourth data interface of the second bus interface to the second data interface of the U.2 interface connector; when the second receiving switching circuit receives a multi-port signal, the second receiving switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

[0021] In an optional implementation, the first transmission switching circuit and the second transmission switching circuit both include: a 2:1 signal multiplexer; the first reception switching circuit and the second reception switching circuit both include: a 1:2 signal demultiplexer.

[0022] In an optional implementation, the port switching circuit further includes: a plurality of signal connectors, wherein the first end of the mode recognition circuit is connected to a bus interface of an external device via a signal connector.

[0023] In an optional implementation, the port switching circuit further includes: a backplane, wherein the mode recognition circuit and the signal connector are both fixed to the backplane.

[0024] In an optional implementation, the clock signal, reset signal, and received and sent data of the external device are all differential interfaces and differential data.

[0025] In a second aspect, the present invention provides a controller, which is applied to a solid-state hard disk. The controller includes: the first aspect and any optional embodiment thereof, including a port switching circuit and a controller body, wherein the controller body includes a first bus interface and a second bus interface, and the first bus interface and the second bus interface are connected to an external device through the port switching circuit.

[0026] The controller of the present invention has a built-in port switching circuit, which identifies the number of external devices connected and determines the bus interface to which the selection circuit is connected. That is, when one external device is connected, only one bus interface is used, and the storage device is in a single-port mode. When multiple external devices are connected, each external device uses a bus interface, and the storage device is in a multi-port mode. Therefore, a single-port / multi-port SSD design is realized on a set of hardware boards, the product specifications of the multi-port SSD are supplemented, and the comprehensive competitiveness of the SSD products is improved.

[0027] In a third aspect, the present invention provides a solid state drive, comprising: a solid state drive controller and a solid state drive body of the second aspect.

[0028] In a fourth aspect, the present invention provides a storage product, comprising: a solid-state hard disk of the third aspect and multiple central processing units, wherein a first end of a pattern recognition circuit is connected to a bus interface of a CPU, and a second end of the pattern recognition circuit is connected to a first end of a selection circuit; a second end of the selection circuit is connected to each bus interface of a storage device; when the pattern recognition circuit recognizes that only one central processing unit is connected, the pattern recognition circuit outputs a single-port signal to the selection circuit, the single-port signal is used to control the selection circuit to send a control signal sent by the central processing unit to each bus interface, and to control the selection circuit to realize a data transmission connection between the central processing unit and any one or specified bus interface; when the pattern recognition circuit recognizes that multiple central processing units are connected, the pattern recognition circuit outputs a multi-port signal to the selection circuit, the multi-port signal is used to control the selection circuit to transmit control signals and data between a central processing unit and a corresponding bus interface.

[0029] The present invention combines a port switching circuit with a storage product. When the CPU of the storage product works in PCIe x2 mode, two ports are output through a selection circuit, and each port transmits information with a bus interface of the storage device, thereby improving the flexibility of the storage product so that it is suitable for various types of hard disk devices.

[0030] In a fifth aspect, the present invention provides a server, comprising: the solid state hard disk of the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 This is a schematic diagram of a PCIe SSD in a related art working in a single-port mode in a server product; Figure 2 It is a schematic diagram of a PCIe SSD in a storage product in the related art working in a multi-port mode; Figure 3 is a composition diagram of a port switching circuit according to an embodiment of the present invention; Figure 4 is a schematic diagram of a single-port mode of a port switching circuit according to an embodiment of the present invention; Figure 5 is a schematic diagram of a dual-port mode of a port switching circuit according to an embodiment of the present invention; Figure 6 is a composition diagram of a gating circuit according to an embodiment of the present invention; Figure 7 is a composition diagram of a signal line switching circuit according to an embodiment of the present invention; Figure 8 is a composition diagram of a clock signal switching circuit according to an embodiment of the present invention; Fig. 9 is a composition diagram of another clock signal switching circuit according to an embodiment of the present invention; Fig.10 is a composition diagram of another clock signal switching circuit according to an embodiment of the present invention; Fig.11 is a composition diagram of another clock signal switching circuit according to an embodiment of the present invention; Fig.12 is a composition diagram of a reset signal switching circuit according to an embodiment of the present invention; Fig.13 is a composition diagram of another reset signal switching circuit according to an embodiment of the present invention; Fig.14 is a composition diagram of another port switching circuit according to an embodiment of the present invention; Fig.15 is a specific circuit structure diagram of a clock signal switching circuit according to an embodiment of the present invention; Fig.16 is a specific circuit structure diagram of a reset signal switching circuit according to an embodiment of the present invention; Fig.17is a composition diagram of a data line switching circuit according to an embodiment of the present invention; Fig.18 is a composition diagram of another data line switching circuit according to an embodiment of the present invention; Fig.19 is a specific circuit structure diagram of a first receiving switching circuit and a second receiving switching circuit according to an embodiment of the present invention; Fig. 20 4 is a specific circuit structure diagram of a first transmission switching circuit and a second transmission switching circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0034] In this embodiment, a port switching circuit is provided, and the port switching circuit is used to realize signal and data transmission between an external device and a storage device. The external device can be a server or a storage product, and the storage device can be a PCIe SSD. The PCIe SSD works in a single-port mode in the server product, that is, the four lanes of the SSD PCIe link are connected to one CPU; and works in a dual-port mode in the storage product, that is, the four lanes of the SSD PCIe link are divided into two groups, two lanes are connected to CPU0, and the other two lanes are connected to the other two CPU1s. The relevant application block diagram is shown in FIG. Figure 1 and Figure 2 shown.

[0035] Generally speaking, SSD controllers support single-port working mode, which is relatively simple to implement in hardware circuits, that is, directly connect the PCIe TX / RX differential signals of 4 lanes, 1 pair of PCIe Clock differential signals, and 1 PCIe Reset signal to the corresponding signals of the single-port SSD. However, when designing the main control of the SSD controller, due to factors such as the area within the chip die and product cost, the SSD main controller cannot support the dual-port working mode. At this time, hardware developers need to flexibly use peripheral hardware circuits and designs to implement the dual-port working mode of the SSD main controller, thereby realizing the product design of the dual-port SSD.

[0036] Based on the above problems, Figure 3 As shown, the port switching circuit includes: a mode recognition circuit and a gating circuit.

[0037] like Figure 3 As shown, the first end of the mode recognition circuit is connected to the bus interface of the external device, the second end of the mode recognition circuit is connected to the first end of the gating circuit; the second end of the gating circuit is connected to each bus interface of the storage device.

[0038] Specifically, the mode recognition circuit can identify the number of connected external devices, and according to the number of external devices, the gating circuit is configured to form a single port or multiple ports, as follows: (1) When the mode recognition circuit recognizes that only one external device is connected, the mode recognition circuit outputs a single-port signal to the strobe circuit, and the single-port signal is used to control the strobe circuit to send the control signal sent by the external device to each bus interface, and to control the strobe circuit to realize the data transmission connection between the external device and any or designated bus interface; (2) When the pattern recognition circuit recognizes that multiple external devices are connected, the pattern recognition circuit outputs a multi-port signal to the selection circuit. The multi-port signal is used to control the selection circuit to transmit control signals and data between an external device and a corresponding bus interface.

[0039] For example, taking the storage device as a PCIe SSD and the external device as a server product, the PCIe SSD includes two bus interfaces, PHY0 and PHY1. The PHY0 bus interface includes four data interfaces, and the PHY1 bus interface includes one data interface. The server product has a built-in central processing unit (CPU), and the CPU works in PCIe x4 mode, that is, the CPU has four data lines. After the pattern recognition circuit recognizes that the CPU is connected, the pattern recognition circuit sends a single-port signal to the enable circuit. The enable circuit connects the four data lines of the CPU to the data interface of PHY0. At the same time, the enable circuit sends the control signals sent by the CPU to PHY0 and PHY1 so that the two bus interfaces are synchronized.

[0040] For example, taking the storage device as a PCIe SSD and the external device as a storage product, the storage product includes two CPUs, CPU0 and CPU1, and each CPU works in PCIe x2 mode, that is, each CPU has 2 data lines. After the pattern recognition circuit recognizes that CPU0 and CPU1 are connected, the pattern recognition circuit sends a multi-port signal to the selection circuit, and the selection circuit connects the 2 data lines of CPU0 to the data interface of PHY0, and the selection circuit connects the 2 data lines of CPU1 to the data interface of PHY1. At the same time, the selection circuit sends all control signals sent by CPU0 to PHY0, and the selection circuit sends all control signals sent by CPU1 to PHY1.

[0041] In some optional embodiments, the bus interface of the external device includes: a clock signal interface, a reset signal interface and multiple data interfaces, wherein the control signal includes: a reset signal and a clock signal, the clock signal interface, the reset signal interface and each data interface of the external device are connected to the first end of the pattern recognition circuit; the external device outputs the clock signal of the bus interface to the pattern recognition circuit through its clock signal interface, the external device outputs the reset signal of the bus interface to the pattern recognition circuit through its reset signal interface, and the external device receives or sends data through its data interface.

[0042] Specifically, the selection circuit sends the reset signal and the clock signal to each bus interface based on the single-port signal, and realizes the data transmission between a corresponding bus interface and the external device; the selection circuit sends the reset signal and the clock signal output by each external device to the corresponding bus interface based on the multi-port signal, and realizes the data transmission between each external device and the corresponding bus interface.

[0043] For example, taking the storage device as a PCIe SSD and the external device as a server product, the selection circuit sends the reset signal and clock signal sent by the CPU to PHY0 and PHY1 based on a single port signal, that is, PHY1 multiplexes the reset signal and clock signal sent by the CPU.

[0044] For example, taking the storage device as a PCIe SSD and the external device as a storage product, the selection circuit sends the reset signal and clock signal sent by CPU0 to PHY0 based on the multi-port signal, and the selection circuit sends the reset signal and clock signal sent by CPU1 to PHY1 based on the multi-port signal.

[0045] In some optional embodiments, the storage device is a controller of a solid-state hard disk, and the controller of the solid-state hard disk includes a first bus interface (i.e., PHY0) and a second bus interface (i.e., PHY1), the first bus interface includes 4 data interfaces, a clock signal interface, and a reset signal interface, the second bus interface includes 2 data interfaces, a clock signal interface, and a reset signal interface, and the pattern recognition circuit includes: a U.2 interface connector, wherein the U.2 interface connector includes a first clock signal interface, a second clock signal interface, a first reset signal interface, a second reset signal interface, an enable output interface, and 4 data interfaces.

[0046] Specifically, Figure 4 , Figure 5 As shown, Figure 4 , Figure 5In the figure, pin 1 of the U.2 interface connector is connected to pin 9 to form a first clock signal interface, pin 2 of the U.2 interface connector is connected to pin 10 to form a first reset signal interface, pin 3 of the U.2 interface connector is connected to pin 11 to form a second clock signal interface, pin 4 of the U.2 interface connector is connected to pin 12 to form a second reset signal interface, pin 5 of the U.2 interface connector is connected to pin 14, pin 6 is connected to pin 15, pin 7 is connected to pin 16, and pin 8 is connected to pin 17 to form four data interfaces, and pin 13 of the U.2 interface connector is an enable output interface.

[0047] Specifically, Figure 4 , Figure 5 In the figure, pin 1 and pin 2 of PHY0 are the clock signal interface and reset signal interface respectively, and pin 3 to pin 6 of PHY0 are data interfaces; pin 1 and pin 2 of PHY1 are the clock signal interface and reset signal interface respectively, and pin 3 and pin 4 of PHY1 are data interfaces.

[0048] Specifically, Figure 4 , Figure 5 In the figure, pin 1 of the selection circuit is connected to pin 9 to form its first clock signal interface, pin 2 of the selection circuit is connected to pin 10 to form its first reset signal interface, pin 3 of the selection circuit is connected to pin 11 to form its second clock signal interface, pin 4 of the selection circuit is connected to pin 12 to form its second reset signal interface, pin 5 of the selection circuit is connected to pin 14, pin 6 is connected to pin 15, pin 7 is connected to pin 16, and pin 8 is connected to pin 17 to form four data interfaces, and pin 13 of the selection circuit is an enable input interface.

[0049] Specifically, if the external device operates in the 4-data bus mode, when the 4 data interfaces of the external device are connected to the 4 data interfaces of the U.2 interface connector, the first clock signal interface and the first reset signal interface of the U.2 interface connector respectively receive the clock signal and the reset signal sent by the external device, enabling the output interface to output a single-port signal. The single-port signal is used to control the selection circuit to send the clock signal and the reset signal sent by the external device to each bus interface. The selection circuit also connects the data interface of the external device to the data interface of the first bus interface through the data interface of the U.2 interface connector.

[0050] For example, the storage device is a PCIe SSD and the external device is a server product. Figure 4As shown, the 1st and 2nd pins of the server product's CPU are the clock signal interface and the reset signal interface respectively, and the 5th to 8th pins of the server product's CPU are 4 data interfaces. When the server product's CPU is connected, the 1st and 2nd pins of the strobe circuit are connected to the 1st and 2nd pins of the CPU via the U.2 interface connector, the 5th to 8th pins of the strobe circuit are connected to the 5th to 8th pins of the CPU via the U.2 interface connector, the 11th and 12th pins of the strobe circuit are also connected to the 1st and 2nd pins of the CPU, and the 14th to 17th pins of the strobe circuit are connected to the 3rd to 6th pins of PHY0.

[0051] Specifically, when the first external device and the second external device operate in a two-data bus mode and the four data interfaces of the two external devices are connected to the four data interfaces of the U.2 interface connector, the first clock signal interface and the first reset signal interface respectively receive the clock signal and the reset signal sent by the first external device, and the second clock signal interface and the second reset signal interface respectively receive the clock signal and the reset signal sent by the second external device, and the selection circuit sends the clock signal and the reset signal sent by the first external device to the first bus interface, and the selection circuit connects the data interface of the first external device with the data interface of the first bus interface through the data interface of the U.2 interface connector, and the selection circuit sends the clock signal and the reset signal sent by the second external device to the second bus interface, and the selection circuit connects the data interface of the second external device with the data interface of the second bus interface through the data interface of the U.2 interface connector.

[0052] For example, the storage device is a PCIe SSD and the external device is a storage product. Figure 5 As shown, pins 1 and 2 of the server product's CPU0 are the clock signal interface and reset signal interface respectively, pins 3 and 4 of the server product's CPU0 are two data interfaces, pins 1 and 2 of CPU1 are the clock signal interface and reset signal interface respectively, and pins 3 and 4 of the server product's CPU1 are two data interfaces. When CPU0 and CPU1 of the storage product are connected, pins 1 and 2 of the enable circuit are connected to pins 1 and 2 of CPU0 through the U.2 interface connector, pins 3 and 4 of the enable circuit are connected to pins 1 and 2 of CPU0 through the U.2 interface connector, pins 5 and 6 of the enable circuit are connected to pins 3 and 4 of CPU1 through the U.2 interface connector, pins 7 and 8 of the enable circuit are connected to pins 3 and 4 of CPU0 through the U.2 interface connector, pins 9 and 10 of the enable circuit are connected to pins 1 and 2 of PHY0 respectively, pins 11 and 12 of the enable circuit are connected to pins 1 and 2 of PHY1 respectively, pins 16 and 17 of the enable circuit are connected to pins 3 and 4 of PHY0 respectively, and pins 14 and 15 of the enable circuit are connected to pins 3 and 4 of PHY1 respectively.

[0053] In some optional embodiments, such as Figure 6 As shown, the gating circuit includes: a signal line switching circuit and a data line switching circuit, Figure 6 Two bus interfaces are taken as an example.

[0054] like Figure 6 As shown, the first end of the signal line switching circuit is connected to each clock signal interface, each reset signal interface, and enable output interface of the U.2 interface connector, and the second end of the signal line switching circuit is connected to each bus interface. Pins 1 to 4 of the signal line switching circuit correspond to Figure 4 , Figure 5 The 1~4 pins of the selection circuit and the 5~8 pins of the signal line switching circuit correspond to Figure 4 , Figure 5 The 9~12 pins of the selection circuit and the 9 pin of the signal line switching circuit correspond to Figure 4 , Figure 5 Pin 13 of the enable circuit.

[0055] Specifically, when the signal line switching circuit receives a single-port signal, the signal line switching circuit sends the clock signal and the reset signal to each bus interface; when the signal line switching circuit receives a multi-port signal, the signal line switching circuit transmits the clock signal and the reset signal sent by the first external device to the first bus interface, and transmits the clock signal and the reset signal sent by the second external device to the second bus interface.

[0056] For example, Figure 6 In the example, the storage device is a PCIe SSD and the external device is a server product. When the server product is connected, pin 9 of the signal line switching circuit receives a single-port signal, pin 1 of the signal line switching circuit receives a clock signal from pin 1 of the CPU through the U.2 interface connector, and pin 2 of the signal line switching circuit receives a reset signal from pin 2 of the CPU through the U.2 interface connector. Both PHY0 and PHY1 receive a clock signal from pin 5 of the signal line switching circuit and a reset signal from pin 7 of the signal line switching circuit, that is, PHY0 and PHY1 multiplex the clock signal and reset signal of the CPU.

[0057] For example, Figure 6In the example, taking the storage device as PCIe SSD and the external device as storage product, when the storage product is connected, pin 9 of the signal line switching circuit receives the multi-port signal, pins 1 and 2 of the signal line switching circuit receive the clock signal and reset signal from pins 1 and 2 of CPU0 through the U.2 interface connector, pins 3 and 4 of the signal line switching circuit receive the clock signal and reset signal from pins 1 and 2 of CPU1 through the U.2 interface connector, PHY0 receives the clock signal and reset signal from pins 5 and 6 of the signal line switching circuit, and PHY1 receives the clock signal and reset signal from pins 7 and 8 of the signal line switching circuit.

[0058] like Figure 6 As shown, the first end of the data line switching circuit is connected to each data interface and the enable output interface of the U.2 interface connector, and the second end of the data line switching circuit is connected to each data interface of each bus interface. Pins 1 to 4 of the data line switching circuit correspond to Figure 4 , Figure 5 The 5th to 8th pins of the selection circuit and the 5th to 8th pins of the data line switching circuit correspond to Figure 4 , Figure 5 The 14~17 pins of the selection circuit and the 9 pin of the data line switching circuit correspond to Figure 4 , Figure 5 Pin 13 of the enable circuit.

[0059] Specifically, when the data line switching circuit receives a single-port signal, the data line switching circuit connects the four data interfaces of the external device to the data interface of the first bus interface through the data interface of the U.2 interface connector; when the data line switching circuit receives a multi-port signal, the data line switching circuit connects the data interface of the first external device to the data interface of the first bus interface through the data interface of the U.2 interface connector, and the data line switching circuit connects the data interface of the second external device to the data interface of the second bus interface through the data interface of the U.2 interface connector.

[0060] For example, Figure 6 In the example, taking the storage device as PCIe SSD and the external device as storage product, when the server product is connected, pin 9 of the data line switching circuit receives the multi-port signal, pins 1 to 4 of the data line switching circuit receive data from pins 1 to 4 of the CPU through the U.2 interface connector, pins 3 to 6 of PHY0 receive data from pins 5 to 8 of the data line switching circuit, and pins 3 to 6 of PHY0 send data to pins 5 to 8 of the data line switching circuit, and pins 1 to 4 of the data line switching circuit send data to pins 1 to 4 of the CPU.

[0061] For example, Figure 6 In the example, taking the storage device as PCIe SSD and the external device as storage product, when the server product is connected, pin 9 of the data line switching circuit receives the multi-port signal, pins 1 and 2 of the data line switching circuit receive data from pins 3 and 4 of CPU1 respectively through the U.2 interface connector, pins 3 and 4 of the data line switching circuit receive data from pins 3 and 4 of CPU0 respectively through the U.2 interface connector, pins 3 and 4 of PHY0 receive data from pins 7 and 8 of the data line switching circuit, pins 3 and 4 of PHY1 receive data from pins 5 and 6 of the data line switching circuit, and at the same time, pins 3 and 4 of PHY0 send data to pins 7 and 8 of the data line switching circuit, pins 3 and 4 of PHY1 send data to pins 5 and 6 of the data line switching circuit, pins 1 and 2 of the data line switching circuit send data to pins 3 and 4 of CPU1, and pins 3 and 4 of the data line switching circuit send data to pins 3 and 4 of CPU1.

[0062] In some optional embodiments, such as Figure 7 As shown, the signal line switching circuit includes: a clock signal switching circuit and a reset signal switching circuit.

[0063] like Figure 7 As shown, the first end of the clock signal switching circuit is connected to each clock signal interface of the U.2 interface connector, the second end of the clock signal switching circuit is connected to the enable output end of the U.2 interface connector, and the third end of the clock signal switching circuit is connected to the clock signal interface of each bus interface. Figure 7 In the figure, pins 1 and 2 of the clock signal switching circuit are equivalent to pins 1 and 3 of the enable circuit, pins 3 and 4 of the clock signal switching circuit are equivalent to pins 9 and 11 of the enable circuit, and pin 5 of the clock signal switching circuit is equivalent to pin 13 of the enable circuit.

[0064] Specifically, when a single-port signal is received, the clock signal switching circuit transmits the clock signal to each bus interface; when a multi-port signal is received, the clock signal switching circuit transmits the clock signal of the first external device to the first bus interface and transmits the clock signal of the second external device to the second bus interface.

[0065] like Figure 7As shown, the first end of the reset signal switching circuit is connected to each reset signal interface of the U.2 interface connector, the second end of the reset signal switching circuit is connected to the enable output end of the U.2 interface connector, and the third end of the reset signal switching circuit is connected to the reset signal interface of each bus interface. Pins 1 and 2 of the reset signal switching circuit are equivalent to pins 2 and 4 of the gating circuit, pins 3 and 4 of the clock signal switching circuit are equivalent to pins 10 and 12 of the gating circuit, and pin 5 of the clock signal switching circuit is equivalent to pin 13 of the gating circuit.

[0066] Specifically, when a single-port signal is received, the reset signal switching circuit transmits the reset signal to each bus interface; when a multi-port signal is received, the reset signal switching circuit transmits the reset signal of the first external device to the first bus interface and transmits the reset signal of the second external device to the second bus interface.

[0067] For example, Figure 7 In the example, the storage device is a PCIe SSD and the external device is a server product. When the server product is connected, pin 5 of the clock signal switching circuit and pin 5 of the reset signal switching circuit receive a single-port signal, pin 1 of the clock signal switching circuit receives the clock signal from pin 1 of the CPU through the U.2 interface connector, and pin 1 of the reset signal switching circuit receives the reset signal from pin 2 of the CPU through the U.2 interface connector. Both PHY0 and PHY1 receive the clock signal from pin 3 of the clock signal switching circuit and the reset signal from pin 3 of the reset signal switching circuit, that is, PHY0 and PHY1 multiplex the clock signal and reset signal of the CPU.

[0068] For example, Figure 7 In the example, taking the storage device as PCIe SSD and the external device as storage product, when the storage product is connected, pin 5 of the clock signal switching circuit and pin 5 of the reset signal switching circuit receive multi-port signals, pin 1 and pin 2 of the clock signal switching circuit receive reset signals from pin 1 of CPU0 and pin 1 of CPU1 respectively through the U.2 interface connector, pin 1 and pin 2 of the reset signal switching circuit receive reset signals from pin 2 of CPU0 and pin 2 of CPU1 respectively through the U.2 interface connector, PHY0 receives the clock signal from pin 3 of the clock signal switching circuit and the reset signal from pin 3 of the reset signal switching circuit, and PHY1 receives the clock signal and reset signal from pin 4 of the clock signal switching circuit and pin 4 of the reset signal switching circuit.

[0069] In some optional embodiments, such as Figure 8 As shown, the clock signal switching circuit includes: 1 clock buffer and 1 2-to-1 clock signal multiplexer.

[0070] like Figure 8As shown, a first end of the clock buffer is connected to a first clock signal interface of the U.2 interface connector, and a second end of the clock buffer is connected to a third end of the 2-to-1 clock signal multiplexer.

[0071] like Figure 8 As shown, the first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

[0072] Specifically, Figure 8 In the figure, pin 1 of the clock buffer is equivalent to pin 1 of the enable circuit, pin 2 of the clock buffer is equivalent to pin 9 of the enable circuit, pin 1 of the 2-to-1 clock signal multiplexer is equivalent to pin 3 of the enable circuit, pin 2 of the 2-to-1 clock signal multiplexer is equivalent to pin 13 of the enable circuit, and pin 4 of the 2-to-1 clock signal multiplexer is equivalent to pin 11 of the enable circuit.

[0073] Specifically, when only the clock buffer receives the clock signal and the 2-to-1 clock signal multiplexer receives a single-port signal, the clock buffer buffers the received clock signal and outputs a homologous clock signal. The clock buffer outputs the homologous clock signal to the first bus interface and the 2-to-1 clock signal multiplexer, and the 2-to-1 clock signal multiplexer sends the homologous clock signal to the second bus interface.

[0074] For example, Figure 8 In the example, the storage device is a PCIe SSD and the external device is a server product. When the server product is connected, PHY0 receives the same clock signal from pin 2 of the clock buffer, pin 2 of the 2-to-1 clock signal multiplexer receives the single-port signal, and pin 4 of the 2-to-1 clock signal multiplexer outputs the same clock signal from pin 2 of the clock buffer, that is, PHY1 receives the same clock signal from pin 2 of the clock buffer.

[0075] Specifically, when the clock buffer receives the clock signal of the first external device, the 2-to-1 clock signal multiplexer receives the clock signal of the second external device, and the 2-to-1 clock signal multiplexer receives a multi-port signal, the clock buffer buffers the received clock signal and outputs a homologous clock signal. The clock buffer outputs the homologous clock signal to the first bus interface and the 2-to-1 clock signal multiplexer, and the 2-to-1 clock signal multiplexer sends the received clock signal of the second external device to the second bus interface.

[0076] For example, Figure 8In the example, the storage device is a PCIe SSD and the external device is a storage product. When the storage product is connected, PHY0 receives the same clock signal from the 2nd pin of the clock buffer, that is, PHY1 receives the clock signal from CPU0. Pin 2 of the 2-to-1 clock signal multiplexer receives the multi-port signal, and pin 4 of the 2-to-1 clock signal multiplexer outputs the same clock signal from pin 11 of the clock buffer U.2 interface connector, that is, PHY1 receives the clock signal from CPU1.

[0077] It should be noted that Figure 8 In the example, for server products, when the server products are connected, since the position of the clock buffer is fixed, pin 1 of the server product CPU needs to be connected to pin 1 of the U.2 interface connector.

[0078] In some optional embodiments, such as Fig. 9 As shown, the clock signal switching circuit includes: a signal through line and a 2-to-1 clock signal multiplexer, wherein: The first end of the signal direct line is connected to the first clock signal interface of the U.2 interface connector, and the second end of the signal direct line is connected to the third end of the 2-to-1 clock signal multiplexer and the clock signal interface of the first bus interface; The first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

[0079] Specifically, when the signal straight-through line receives the clock signal of an external device and the 2-to-1 clock signal multiplexer receives a single-port signal, the signal straight-through line transmits the clock signal to PHY0 and the 2-to-1 clock signal multiplexer, and the 2-to-1 clock signal multiplexer transmits the clock signal to PYH1; specifically, when the signal straight-through line and the 2-to-1 clock signal multiplexer both receive clock signals, and the 2-to-1 clock signal multiplexer receives a multi-port signal, that is, the first external device is connected to the first clock signal interface of the U.2 interface connector, and the second external device is connected to the second clock signal interface of the U.2 interface connector, the signal straight-through line transmits the clock signal of the first external device to PHY0, and the 2-to-1 clock signal multiplexer transmits the clock signal of the second external device to PHY1.

[0080] In some optional embodiments, such as Fig.10 As shown, the clock signal switching circuit includes: a first clock buffer, a second clock buffer, a first 2-to-1 clock multiplexer, and a second 2-to-1 clock multiplexer.

[0081] like Fig.10As shown, the first end of the first clock buffer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first clock buffer is connected to the clock signal interface of the first bus interface, and the second end of the first clock buffer is connected to the third end of the second 2-to-1 clock multiplexer; like Fig.10 As shown, the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first 2-to-1 clock multiplexer is connected to the clock signal interface of the first bus interface; like Fig.10 As shown, the first end of the second clock buffer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second clock buffer is connected to the clock signal interface of the second bus interface, and the second end of the second clock buffer is connected to the third end of the first 2-to-1 clock multiplexer; like Fig.10 As shown, the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface; Specifically, when the clock signal interface of the external device is only connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first clock buffer buffers the received clock signal and outputs a homologous clock signal, the first clock buffer sends the homologous clock signal to the second 2-to-1 clock multiplexer and the first bus interface, and the second 2-to-1 clock multiplexer sends the homologous clock signal to the second bus interface.

[0082] For example, Fig.10 In the example, when the storage device is a PCIe SSD and the external device is a server product, when pins 1 and 2 of the CPU are connected to pins 1 and 2 of the U.2 interface connector, that is, the first clock buffer receives the clock signal from the CPU, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first clock buffer outputs the same-source clock signal to PHY0 and the second 2-to-1 clock multiplexer. The single-port signal locks the first 2-to-1 clock multiplexer and unlocks the second 2-to-1 clock multiplexer, and the second 2-to-1 clock multiplexer sends the same-source clock signal to PHY1.

[0083] Specifically, when the clock signal interface of the external device is only connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the second clock buffer buffers the received clock signal and outputs the same source clock signal, the second clock buffer sends the same source clock signal to the first 2-to-1 clock multiplexer and the second bus interface, the first 2-to-1 clock multiplexer sends the same source clock signal to the first bus interface, and the single-port signal locks the second 2-to-1 clock multiplexer and unlocks the first 2-to-1 clock multiplexer.

[0084] For example, Fig.10 In the example, when the storage device is a PCIe SSD and the external device is a server product, when pins 1 and 2 of the CPU are connected to pins 3 and 4 of the U.2 interface connector, that is, the second clock buffer receives the clock signal from the CPU, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the second clock buffer outputs the same-source clock signal to PHY1 and the first 2-to-1 clock multiplexer. The single-port signal locks the second 2-to-1 clock multiplexer and unlocks the first 2-to-1 clock multiplexer. The first 2-to-1 clock multiplexer sends the same-source clock signal to PHY0.

[0085] Specifically, when the clock signal interface of the first external device is connected to the first clock signal interface of the U.2 interface connector, the clock signal interface of the second external device is connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive multi-port signals, the first clock buffer outputs the same source clock signal of the clock signal of the first external device to the first bus interface, and the second clock buffer outputs the same source clock signal of the clock signal of the second external device to the second bus interface.

[0086] For example, Fig.10 In the example, taking the storage device as PCIe SSD and the external device as storage product, when pins 1 and 2 of CPU0 are connected to pins 1 and 2 of U.2 interface, and pins 1 and 2 of CPU1 are connected to pins 3 and 4 of U.2 interface, that is, the first clock buffer receives the clock signal of CPU0, and the second clock buffer receives the clock signal of CPU1 at the same time, the multi-port signal locks the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer, and the first clock buffer sends the same source clock signal of CPU0 clock signal to PHY0, and the second clock buffer sends the same source clock signal of CPU1 clock signal to PHY1.

[0087] It should be noted that Fig.10In the case of a server product, when pins 1 and 2 of the CPU are connected to pins 1 and 2 of the U.2 interface connector, or to pins 3 and 4 of the U.2 interface connector, the U.2 interface connector can identify that only one CPU is connected.

[0088] In some optional embodiments, such as Fig.11 As shown, the clock signal switching circuit includes: a first 2-to-1 clock multiplexer and a second 2-to-1 clock multiplexer.

[0089] like Fig.11 As shown, the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the first 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, and the fourth end of the first 2-to-1 clock multiplexer is connected to the clock signal interface of the first bus interface.

[0090] like Fig.11 As shown, the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the second 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface.

[0091] When the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface.

[0092] Specifically, when the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface.

[0093] For example, Fig.11In the embodiment, when the clock signal interface of the CPU is connected to pin 9 of the U.2 interface connector, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, and both the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive the clock signal of the CPU. Then, the first 2-to-1 clock multiplexer sends the clock signal to CPU0, and the second 2-to-1 clock multiplexer sends the clock signal to CPU1.

[0094] Specifically, when the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface.

[0095] For example, Fig.11 In the example, when the clock signal interface of the CPU is connected to pin 11 of the U.2 interface connector, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, and both the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive the clock signal of the CPU. Then, the first 2-to-1 clock multiplexer sends the clock signal to CPU0, and the second 2-to-1 clock multiplexer sends the clock signal to CPU1.

[0096] Specifically, when the clock signal interface of the first external device and the clock signal interface of the second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive multi-port signals, the first 2-to-1 clock multiplexer outputs the clock signal of the first external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the second external device to the second bus interface.

[0097] For example, Fig.11 In the embodiment, when the clock signal interface of CPU0 is connected to pin 9 of the U.2 interface connector and the clock signal interface of CPU1 is connected to pin 11 of the U.2 interface connector, at this time, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer receives the clock signal of CPU0 and the second 2-to-1 clock multiplexer receives the clock signal of CPU1, then the first 2-to-1 clock multiplexer sends the clock signal of CPU0 to CPU0, and the second 2-to-1 clock multiplexer sends the clock signal of CPU1 to CPU1.

[0098] It should be noted that for Fig.10 , Fig.11In the structure shown, under normal circumstances, when only one CPU is connected, due to the U.2 interface specification and related protocols in the solid-state drive, the CPU can only be connected to pin 9 of the U.2 interface connector. However, for the case where the CPU is connected to pin 11 of the U.2 interface connector, it can also be achieved by adaptively modifying the related protocols.

[0099] In some optional embodiments, such as Fig.12 As shown, the reset signal switching circuit includes: 1 signal through line and 1 reset signal multiplexer.

[0100] like Fig.12 As shown, the first end of the signal straight-through line is connected to the first reset signal interface of the U.2 interface connector, and the second end of the signal straight-through line is connected to the reset signal interface of the first bus interface; the first end of the reset signal multiplexer is connected to the second reset signal interface of the U.2 interface connector, the second end of the reset signal multiplexer is connected to the first end of the signal straight-through line, the third end of the reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the reset signal multiplexer is connected to the reset signal interface of the second bus interface.

[0101] Specifically, when the signal pass-through line receives a reset signal and the reset signal multiplexer receives a single-port signal, the signal pass-through line transmits the reset signal to the first bus interface and the reset signal multiplexer, and each reset signal multiplexer sends the reset signal transmitted by the signal pass-through line to the second bus interface.

[0102] For example, Fig.12 In the example, taking the storage device as PCIe SSD and the external device as server product, when pins 1 and 2 of the CPU are connected to pins 1 and 2 of the U.2 interface connector, that is, the signal pass-through line receives the reset signal of the CPU, and the reset signal multiplexing receives the single-port signal, the reset signal multiplexer multiplexes the reset signal of the CPU to PHY1.

[0103] Specifically, when the signal direct line receives the reset signal of the first external device and the reset signal multiplexer receives the reset signal of the second external device and the multi-port signal, the signal direct line transmits the reset signal to the first bus interface and the reset signal multiplexer, and the reset signal multiplexer transmits the reset signal of the second external device to the second bus interface.

[0104] For example, Fig.12In the example, taking the storage device as PCIe SSD and the external device as server product, when pins 1 and 2 of CPU0 are connected to pins 1 and 2 of the U.2 interface connector, and pins 1 and 2 of CPU1 are connected to pins 3 and 4 of the U.2 interface connector, that is, the signal pass-through line receives the reset signal of CPU0, the reset signal multiplexer receives the single-port signal, the reset signal multiplexer receives the single-port signal and the reset signal of CPU1, then the reset signal multiplexer multiplexes the reset signal of CPU1 to PHY1.

[0105] In some optional embodiments, such as Fig.13 As shown, the reset signal switching circuit includes: a first reset signal multiplexer and a second reset signal multiplexer.

[0106] like Fig.13 As shown, the first end and the second end of the first reset signal multiplexer are connected to the first reset signal interface and the second reset signal interface of the U.2 interface connector, the third end of the first reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first reset signal multiplexer is connected to the reset signal interface of the first bus interface.

[0107] like Fig.13 As shown, the first end and the second end of the second reset signal multiplexer are connected to the second reset signal interface and the first reset signal interface of the U.2 interface connector, the third end of the second reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second reset signal multiplexer is connected to the reset signal interface of the second bus interface.

[0108] Specifically, when the reset signal interface of the external device is connected to the first reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface.

[0109] For example, Fig.13 In the example, when the storage device is a PCIe SSD and the external device is a server product, when pins 1 and 2 of the CPU are connected to pins 1 and 2 of the U.2 interface connector, that is, the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal and a reset signal of the CPU, the first reset signal multiplexer sends the reset signal of the CPU to PHY0, and the second reset signal multiplexer sends the reset signal of the CPU to PHY1.

[0110] Specifically, when the reset signal interface of the external device is connected to the second reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface.

[0111] For example, Fig.13 In the example, when the storage device is a PCIe SSD and the external device is a server product, when pins 1 and 2 of the CPU are connected to pins 3 and 4 of the U.2 interface connector, that is, the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal and a reset signal of the CPU, the first reset signal multiplexer sends the reset signal of the CPU to PHY0, and the second reset signal multiplexer sends the reset signal of the CPU to PHY1.

[0112] Specifically, when the reset signal interface of the first external device and the reset signal interface of the second external device are respectively connected to the first reset signal interface and the second reset signal interface connected to the U.2 interface, and the first reset signal multiplexer and the second reset signal multiplexer receive multi-port signals, the first reset signal multiplexer outputs the reset signal of the first external device to the first bus interface, and the second reset signal multiplexer outputs the reset signal of the second external device to the second bus interface.

[0113] For example, Fig.13 In the example, when the storage device is a PCIe SSD and the external device is a server product, when pins 1 and 2 of CPU0 are connected to pins 1 and 2 of the U.2 interface connector, and pins 1 and 2 of CPU1 are connected to pins 3 and 4 of the U.2 interface connector, that is, the first reset signal multiplexer receives a single-port signal and the reset signal of CPU0, and the second reset signal multiplexer receives a single-port signal and the reset signal of CPU1, the first reset signal multiplexer sends the reset signal of CPU0 to PHY0, and the second reset signal multiplexer sends the reset signal of CPU1 to PHY1.

[0114] It should be noted that Fig.13 In the case where only one CPU is connected, the U.2 interface connector can be recognized regardless of whether pins 1 and 2 of the CPU are connected to pins 1 and 2 of the U.2 interface connector, or pins 1 and 2 of the CPU are connected to pins 3 and 4 of the U.2 interface connector.

[0115] It should be noted that for Fig.13In the structure shown, under normal circumstances, when only one CPU is connected, due to the U.2 interface specification and related protocols in the solid-state drive, the CPU can only be connected to pin 10 of the U.2 interface connector. However, for the case where the CPU is connected to pin 12 of the U.2 interface connector, it can also be achieved by adaptively modifying the related protocols.

[0116] based on Figure 8 , Fig.11 , the structure of the port switching circuit is as follows Fig.14 As shown, Fig.14 In the U.2 interface connector, the single / dual port enable output signal DUALPORTEN_n is used to output high and low levels respectively, where the high level corresponds to the single-port signal and the low level corresponds to the multi-port signal. For different types of product access, there are the following two situations: (1) In the server system, the DUALPORTEN_n signal outputs a high level, and one CPU in the server system works in PCIe x4 mode. At this time, the relevant communication signals passing through the U.2 interface connector are 1 differential PCIe clock signal PCIe_CLK0_P / N, 1 PCIe reset signal PCIe_RST0_n, 1 single port output enable signal DUALPORTEN_n, and 4 PCIe communication signals PCIe0~PCIe3. Since the single / dual port enable output signal DUALPORTEN_n is a high level, the 1:2 PCIe Clock Buffer outputs the same source clock signal. After passing through the 2:1 PCIe Clock Muxer, the differential clock signals of the SSD controller PHY0 and PHY1 share the PCIe_CLK0_P / N signal from the server side. At the same time, after the single PCIe_RST0_n signal from the server side passes through the 2:1 Single Muxer, the reset signals of the SSD controller PHY0 and PHY1 share this signal. At this time, the two groups of PCIe2 and PCIe3 signals at the U.2 interface connector are connected to the two groups of PCIe signals at Lane2 and Lane3 of the PHY0 on the SSD controller through the 1:2 PCIe SingleDemuxer, 2:1 PCIe Single Muxer and single-port output enable signal. In short, in single-port mode, the server system realizes the connection and communication with the PCIe signal link inside the PHY0 of the SSD controller.

[0117] (2) In the storage system, the single / dual port enable output signal DUALPORTEN_n outputs a low level, and the two CPUs in the storage system work in PCIe x2 mode respectively. At this time, the relevant communication signals passing through the U.2 interface connector are 2 differential PCIe clock signals PCIe_CLK0_P / N and PCIe_CLK1_P / N, 2 PCIe reset signals PCIe_RST0_n and PCIe_RST1_n, 1 dual port output enable signal DUALPORTEN_n, and 4 PCIe communication signals PCIe0~PCIe3. Since the DUALPORTEN_n signal is at a low level, the 1:2 PCIe Clock Buffer outputs the same source clock signal. After passing through the 2:1 PCIe Clock Muxer, the differential clock signals of the SSD controller PHY0 and PHY1 come from the PCIe_CLK0_P / N signal and PCIe_CLK1_P / N of the two CPUs of the storage system, respectively. At the same time, after the single-channel PCIe_RST0_n signal from the storage system side passes through the 2:1 Single Muxer, the reset signals of the SSD controller PHY0 and PHY1 come from the PCIe_RST0_n and PCIe_RST1_n of the two CPUs of the storage system, respectively. At this time, the two groups of PCIe2 and PCIe3 signals at the U.2 connector end are connected to the two groups of PCIe signals at the Lane0 and Lane1 ends of the PHY1 on the SSD controller chip through the 1:2 PCIeSingle Demuxer, 2:1 PCIe Single Muxer and the dual-port output enable signal. In summary, in dual-port mode, the PCIe0~PCIe3 of the two CPUs of the storage system are connected and communicated with the internal PCIe signal links of PHY0 (Lane0~Lane1) and PHY1 (Lane2~Lane3) of the SSD controller respectively.

[0118] Fig.14 In the example, the clock buffer and 2-to-1 clock signal multiplexer use the PCIe3.0 ClockBuffer device 9DBV0231 and Clock Muxer device 9DMV0141 from IDT respectively. Fig.15 shown.

[0119] The CLK_IN input pin of the Clock Buffer device 9DBV0231 is connected to the clock signal PCIe_CLK0_P / N at the U.2 interface connector. The peripheral control pins are correctly configured (for example: Fig.15vOE(1:0) in the 2-way clock signal indicates the enable signal, which is pulled down by 10K resistors by default, that is, R1 and R2 resistors are pulled down to ground. The SMbus branch of this chip is not processed by default, so the SDATA_3.3 and SCLK_3.3 peripheral circuits do not process it. CKPWRGD_PD# indicates that the low level of the enable will put the chip into low power consumption mode. This pin is pulled up to 1.8V power level through R3. vHIBW_BYPM_LOBW# indicates the default working state of PLL. The application circuit divides the pin by two 10K resistors R4 and R5 to set the chip in bypass working mode) and when the power supply pin is powered, it outputs two differential clock signals DIF1 and DIF0, where DIF1 is connected to one differential clock signal PCIe0_CLK_P / N of SSD controller PHY0, and DIF0 is connected to one differential clock input signal DIF_INA of Clock Muxer device. Of course, the hardware connection relationship between DIF1 and DIF0 can be adjusted according to PCB layout and wiring.

[0120] The other differential clock input signal DIF_INB of the Clock Muxer device is connected to the clock signal PCIe_CLK1_P / N at the U.2 interface connector, and the differential clock output signal DIF0 is connected to the differential clock signal PCIe1_CLK_P / N of the SSD controller PHY1. Correctly configure the peripheral control pins (for example: Fig.15In the figure, OE0# represents the output enable signal. By default, this pin is pulled down to ground through the R7 10K resistor; vSW_MODE represents the switch mode signal. By default, this pin is pulled down to ground through the R6 10K resistor, indicating the asynchronous working mode) and the power pin is powered, the SEL_A_B# pin is connected to the single / dual port signal DUALPORTEN_n at the U.2 connector end: when DUALPORTEN_n outputs a high level, that is, the single-port mode, at this time, the differential output clock signal DIF0 of the ClockMuxer device selects the signal at the DIF_INA end, that is, the PCIe_CLK0_P / N signal of the U.2 interface connector; when DUALPORTEN_n outputs a low level, that is, the dual-port mode, at this time, the differential output clock signal DIF0 of the Clock Muxer device selects the signal at the DIF_INB end, that is, the PCIe_CLK1_P / N signal of the U.2 port. In summary, when the SSD works in single-port mode (DUALPORTEN_n outputs a high level), the differential clock signals PCIe0_CLK_P / N and PCIe1_CLK_P / N of PHY0 and PHY1 of the SSD controller come from the same-source clock signal PCIe_CLK0_P / N; when the SSD works in dual-port mode (DUALPORTEN_n outputs a low level), the differential clock signals PCIe0_CLK_P / N and PCIe1_CLK_P / N of PHY0 and PHY1 of the SSD controller come from non-same-source clock signals PCIe_CLK0_P / N and PCIe_CLK1_P / N, respectively.

[0121] For the reset switching circuit working in single and dual ports, the detailed circuit is as follows Fig.16 shown. Fig.16 Select TI's 2:1 Signal Muxer device TMUX154E, connect the A0 input to the PCIe_RST1_n signal of the U.2 interface connector, the A1 input to the PCIe_RST0_n signal of the U.2 connector and the PCIe reset signal PCIe0_RSTn input at the PHY0 end of the SSD controller, and the A output to the PCIe reset signal PCIe1_RSTn input at the PHY1 end of the SSD controller. Configure the peripheral control pins correctly (for example: Fig.16In the figure, EN_n represents the output enable signal, which is pulled down to ground by the R8 10K resistor by default) and the power pin, the SEL pin is connected to the single / dual port signal DUALPORTEN_n at the U.2 connector end: when DUALPORTEN_n outputs a high level, that is, single-port mode, at this time the output signal A of the Signal Muxer device selects the signal at the A1 end, that is, the PCIe_RST0_n signal of the U.2 interface connector; when DUALPORTEN_n outputs a low level, that is, dual-port mode, at this time the output signal A of the Signal Muxer device selects the signal at the A0 end, that is, the PCIe_RST1_n signal of the U.2 interface connector. In summary, when the SSD works in single-port mode (DUALPORTEN_n outputs a high level), the PCIe reset signals PCIe0_RSTn and PCIe1_RSTn of PHY0 and PHY1 of the SSD controller come from the reset signal PCIe_RST0_n of the same source; when the SSD works in dual-port mode (DUALPORTEN_n outputs a low level), the PCIe reset signals PCIe0_RSTn and PCIe1_RSTn of PHY0 and PHY1 of the SSD controller come from reset signals PCIe_RST0_n and PCIe_RST1_n of different sources, respectively.

[0122] In some optional implementations, the U.2 interface connector data interface is a first data interface, a second data interface, a third data interface, and a fourth data interface, the data interface of the first bus interface includes: a first data interface, a second data interface, a third data interface, and a fourth data interface, and the data interface of the second bus interface includes: a first data interface, a second data interface, such as Fig.17 As shown, the data line switching circuit includes: a first data direct line, a second data direct line, a first data line switching sub-circuit, and a second data line switching sub-circuit.

[0123] Specifically, the first data through line connects the first data interface of the U.2 interface connector with the first data interface of the first bus interface; the second data through line connects the second data interface of the U.2 interface connector with the second data interface of the first bus interface.

[0124] Specifically, the first end of the first data circuit switching subcircuit is connected to the third data interface of the U.2 interface connector, the second end of the first data circuit switching subcircuit is connected to the enable output port of the U.2 interface connector, and the third end of the first data circuit switching subcircuit is connected to the third data interface of the first bus interface and the first data interface of the second bus interface; the first end of the second data circuit switching subcircuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second data circuit switching subcircuit is connected to the enable output port of the U.2 interface connector, and the third end of the second data circuit switching subcircuit is connected to the fourth data interface of the first bus interface and the second data interface of the second bus interface.

[0125] Specifically, if the external device operates in the 4-data bus mode, when the 4 data interfaces of the external device are connected to the 4 data interfaces of the U.2 interface connector, the first data line switching subcircuit connects the third data interface of the U.2 interface connector with the third data interface of the first bus interface, and connects the fourth data interface of the U.2 interface connector with the fourth data interface of the first bus interface.

[0126] For example, taking the storage device as a PCIe SSD and the external device as a server product, when the CPU is connected, the data interface of PHY0 is connected to the 16th and 17th pins of the U.2 interface connector, the first data line switching subcircuit, and the second data switching subcircuit, that is, PHY0 transmits data with the CPU.

[0127] Specifically, when the first external device and the second external device operate in a two-data bus mode, the two data interfaces of the first external device are connected to the first data interface and the second data interface of the U.2 interface connector, and the two data interfaces of the second external device are connected to the third data interface and the fourth data interface of the U.2 interface connector, the first data line switching subcircuit connects the third data interface of the U.2 interface connector to the first data interface of the second bus interface, and connects the fourth data interface of the U.2 interface connector to the second data interface of the second bus interface.

[0128] For example, taking the storage device as a PCIe SSD and the external device as a storage product, when CPU0 and CPU1 are connected, the data interface of PHY0 is connected to the 16th and 17th pins of the U.2 interface connector, and the data interface of PHY1 is connected to the first data line switching subcircuit and the second data switching subcircuit, that is, CPU0 transmits data with PHY0, and CPU1 transmits data with PHY1.

[0129] In some optional implementations, the first data line switching sub-circuit includes: a first sending switching circuit and a first receiving switching circuit.

[0130] A first end of the first transmission switching circuit is connected to the third data interface of the first bus interface, a second end of the first transmission switching circuit is connected to the first data interface of the second bus interface, a third end of the first transmission switching circuit is connected to the third data interface of the U.2 interface connector, and a fourth end of the first transmission switching circuit is connected to the enable output port of the U.2 interface connector; A first end of the first receiving switching circuit is connected to the third data interface of the U.2 interface connector, a second end of the first receiving switching circuit is connected to the enable output port of the U.2 interface connector, a third end of the first receiving switching circuit is connected to the third data interface of the first bus interface, and a fourth end of the first receiving switching circuit is connected to the first data interface of the second bus interface; When the first transmission switching circuit receives a single-port signal, the first transmission switching circuit connects the third data interface of the first bus interface to the third data interface of the U.2 interface connector; when the first transmission switching circuit receives a multi-port signal, the first transmission switching circuit connects the first data interface of the second bus interface to the third data interface of the U.2 interface connector; When the first receiving switching circuit receives a single-port signal, the first receiving switching circuit connects the third data interface of the first bus interface to the third data interface of the U.2 interface connector; when the first receiving switching circuit receives a multi-port signal, the first receiving switching circuit connects the first data interface of the second bus interface to the third data interface of the U.2 interface connector.

[0131] In some optional implementations, the second data line switching sub-circuit includes: a second sending switching circuit and a second receiving switching circuit.

[0132] A first end of the second transmission switching circuit is connected to the fourth data interface of the first bus interface, a second end of the second transmission switching circuit is connected to the second data interface of the second bus interface, a third end of the second transmission switching circuit is connected to the fourth data interface of the U.2 interface connector, and a fourth end of the second transmission switching circuit is connected to the enable output port of the U.2 interface connector; A first end of the second receiving switching circuit is connected to the fourth data interface of the U.2 interface connector, a second end of the second receiving switching circuit is connected to the enable output port of the U.2 interface connector, a third end of the second receiving switching circuit is connected to the fourth data interface of the first bus interface, and a fourth end of the second receiving switching circuit is connected to the second data interface of the second bus interface; When the second sending switching circuit receives a single-port signal, the second sending switching circuit connects the fourth data interface of the first bus interface to the fourth data interface of the U.2 interface connector; when the second sending switching circuit receives a multi-port signal, the second sending switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

[0133] When the second receiving switching circuit receives a single-port signal, the second receiving switching circuit connects the fourth data interface of the second bus interface to the second data interface of the U.2 interface connector; when the second receiving switching circuit receives a multi-port signal, the second receiving switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

[0134] Optionally, refer to Fig.18 The first sending switching circuit and the second sending switching circuit both include: a 2:1 signal multiplexer; the first receiving switching circuit and the second receiving switching circuit both include: a 1:2 signal demultiplexer.

[0135] Fig.18In the embodiment, PCIe0_Tp / Tn, PCIe0_Rp / Rn, PCIe1_Tp / Tn, PCIe1_Rp / Rn and other PCIe signals of the U.2 interface connector are respectively connected to the PCIe signals of Lane0_Rp / Rn, Lane0_Tp / Tn, Lane1_Rp / Rn, Lane1_Tp / Tn and other PCIe signals of the SSD controller PHY0. PCIe2_Tp / Tn, PCIe3_Tp / Tn of the U.2 interface connector are respectively connected to the PCIe signals of Lane2_Rp / Rn, Lane0_Rp / Rn of PHY1 and other PCIe signals of the SSD controller PHY0 and other PCIe signals of Lane3_Rp / Rn, Lane1_Rp / Rn of PHY1 and other PCIe signals of the SSD controller PHY0 through two PCIe signals output by the 1:2 PCIe signal demuxer device. The two PCIe signals of Lane2_Tp / Tn of PHY0 and Lane0_Tp / Tn of PHY1 and the two PCIe signals of Lane3_Tp / Tn of PHY0 and Lane3_Tp / Tn of PHY1 of the SSD controller are connected to the PCIe2_Rp / Rn and PCIe3_Rp / Rn signals of the U.2 connector through the 2:1 PCIe signal Muxer device. DUALPORTEN_n is used as a switch enable signal to control the channel selection of the 1:2 PCIe signal Demuxer device and the 2:1 PCIe signal Muxer device. When DUALPORTEN_n outputs a high level, PCIe2_Tp / Tn, PCIe3_Tp / Tn of the U.2 interface connector are connected to Lane2_Rp / Rn, Lane3_Rp / Rn signals of the SSD controller PHY0, and PCIe2_Rp / Rn, PCIe3_Rp / Rn of the U.2 interface connector are connected to Lane2_Tp / Tn, Lane3_Tp / Tn signals of the SSD controller PHY0; that is, the 4 PCIe signals on the server side communicate with the 4 groups of PCIe signals inside the SSD controller PHY0. When DUALPORTEN_n outputs a low level, the PCIe2_Tp / Tn and PCIe3_Tp / Tn of the U.2 interface connector are connected to the Lane0_Rp / Rn and Lane1_Rp / Rn signals of PHY1 of the SSD controller, and the PCIe2_Rp / Rn and PCIe3_Rp / Rn of the U.2 interface connector are connected to the Lane0_Tp / Tn and Lane1_Tp / Tn signals of PHY1 of the SSD controller; that is, the two PCIe signals of the two CPUs of the storage device communicate with the two groups of PCIe signals of the SSD controllers PHY0 and PHY1 respectively.

[0136] Alternatively, if Fig.19As shown, the 1:2 signal demultiplexer uses TI's integrated 1:2 4-way signal separator DS160PR412, and this application circuit uses 2 of them. Among them, the 2 PCIe transmission signals PCIe2_Tp, PCIe2_Tn and PCIe3_Tp, PCIe3_Tn of the U.2 connector are respectively connected to the 2 PCIe transmission signals RX0P, RX0N and RX1P, RX1N of the chip; the A port TXA0P, TXA0N and the B port TXB0P, TXB0N of the 2 PCIe TX signals of channel 0 of the chip are respectively connected to Lane0_Rp, Lane0_Rn of the SSD controller PHY1 and Lane2_Rp, Lane2_Rn of PHY0; the A port TXA1P, TXA1N and the B port TXB1P, TXB1N of the 2 PCIe TX signals of channel 1 of the chip are respectively connected to Lane1_Rp, Lane1_Rn of the SSD controller PHY1 and Lane3_Rp, Lane3_Rn of PHY0.

[0137] The other pins of the chip are for power and configuration functions, where VCC supplies power to P3V3 and is filtered by C11uF and C2 0.1uF. VREG1 and VREG2 represent the voltage outputs inside the chip, which are decoupled by C3 0.22uF and C4 0.22uF respectively. The PD pin is pulled down to GND through the R9 10K resistor, indicating that the chip is in power-on working mode, not in power-off mode; the MODE pin is a mode configuration function. In this embodiment, the pin is pulled down to GND through the R10 1K resistor. At this time, other EQ0, EQ1, GAIN, and RX_EXT are used as power-on configuration pins to control the function of the chip; the RX_EXT pin is configured in a floating state, indicating that the chip handles the normal PCIe working mode; the GAIN pin is configured in a floating state, indicating that the flat gain of the entire data path is set; the EQ0 and EQ1 pins are pulled down to GND through the R11 and R12 resistors respectively. R11 and R12 can select 1K, 13K, 59K and other resistance values ​​or floating processing methods. In actual tests, the internal equalization parameters of the chip can be adjusted by selecting different resistance values, and high-frequency boost is used to balance the frequency-related insertion loss effect of the passive channel.

[0138] In addition, the DUALPORTEN_n signal at the U.2 connector end is connected one by one with the port selection signal SEL of the chip and the GPIO signal at the SSD controller end. When the DUALPORTEN_n signal outputs a high level, the PCIe receiving signals RX0P and RX0N of channel 0 of the chip select the PCIe transmitting signals TXB0P and TXB0N of port B, and the PCIe receiving signals RX1P and RX1N of channel 1 of the chip select the PCIe transmitting signals TXB1P and TXB1N of port B. That is, the PCIe2 signal and PCIe3 signal from the server end communicate with Lan2 and Lane3 of the SSD controller PHY0 respectively. At this time, the SSD controller works in single-port mode. When the DUALPORTEN_n signal outputs a low level, the PCIe receiving signals RX0P and RX0N of channel 0 of the chip select the PCIe sending signals TXA0P and TXA0N of port A, and the PCIe receiving signals RX1P and RX1N of channel 1 of the chip select the PCIe sending signals TXA1P and TXA1N of port A, that is, the PCIe2 signal and PCIe3 signal from the storage device end communicate with Lan0 and Lane1 of the SSD controller PHY1 respectively. At this time, the SSD controller works in dual-port mode.

[0139] Alternatively, if Fig. 20 As shown, the 2:1 signal multiplexer uses an integrated 2:1 4-way signal multiplexer DS160PR421 from TI, and the first transmission switching circuit and the second transmission switching circuit use 2 of the ways. Among them, the TX0P and TX0N signals of the chip's 2-way PCIe transmission signal channel 0 and the RX1P and RX1N signals of channel 1 are respectively connected to the 2-way PCIe receiving signals PCIe2_Rp, PCIe2_Rn and PCIe3_Rp, PCIe3_Rn of the U.2 connector one by one; the A port RXA0P and RXA0N and the B port RXB0P and RXB0N of the 2-way PCIe receiving signals of channel 0 of the chip are respectively connected to the PCIe transmission signals Lane0_Tp and Lane0_Tn of the SSD controller PHY1 and the PCIe transmission signals Lane2_Tp and Lane2_Tn of PHY0; the A port RXA1P and RXA1N and the B port RXB1P and RXB1N of the 2-way PCIe receiving signals of channel 1 of the chip are respectively connected to the PCIe The transmission signals Lane1_Tp and Lane1_Tn and the PCIe transmission signals Lane3_Tp and Lane3_Tn of PHY0 are connected one by one.

[0140] The other pins of the chip are for power and configuration functions, where VCC supplies power to P3V3 and is filtered by C51uF and C6 0.1uF. VREG1 and VREG2 represent the voltage outputs inside the chip, which are decoupled by C7 0.22uF and C8 0.22uF respectively. The PD pin is pulled down to GND through the R16 10K resistor, indicating that the chip is in power-on working mode, not power-off mode; the MODE pin is a mode configuration function. In the patent embodiment, the pin is pulled down to GND through the R13 1K resistor. At this time, the other EQ0, EQ1, GAIN, and RX_EXT are used as power-on configuration pins to control the function of the chip; the RX_EXT pin is configured in a floating state, indicating that the chip handles the normal PCIe working mode; the GAIN pin is configured in a floating state, indicating that the flat gain of the entire data path is set; the EQ0 and EQ1 pins are pulled down to GND through the R14 and R15 resistors respectively. R14 and R15 can select 1K, 13K, 59K and other resistance values ​​or be suspended. In actual tests, the internal equalization parameters of the chip can be adjusted by selecting different resistance values, and high-frequency boost is used to balance the frequency-related insertion loss effect of the passive channel.

[0141] In addition, the DUALPORTEN_n signal at the U.2 connector end is connected one by one with the port selection signal SEL of the chip and the GPIO signal at the SSD controller end. When the DUALPORTEN_n signal outputs a high level, the PCIe sending signals RX0P and RX0N of channel 0 of the chip select the PCIe sending signals RXB0P and RXB0N of port B, and the PCIe sending signals TX1P and TX1N of channel 1 of the chip select the PCIe sending signals RXB1P and RXB1N of port B. That is, the PCIe2 signal and PCIe3 signal from the server end communicate with Lan2 and Lane3 of the SSD controller PHY0 respectively. At this time, the SSD controller works in single-port mode. When the DUALPORTEN_n signal outputs a low level, the PCIe transmit signals TX0P and TX0N of channel 0 of the chip select the PCIe receive signals RXA0P and RXA0N of port A, and the PCIe transmit signals TX1P and TX1N of channel 1 of the chip select the PCIe receive signals RXA1P and RXA1N of port A, that is, the PCIe2 signal and PCIe3 signal from the storage device communicate with Lan0 and Lane1 of the SSD controller PHY1 respectively. At this time, the SSD controller works in dual-port mode.

[0142] This embodiment starts from the actual SSD controller, utilizes the signal characteristics of the PCIe interface of the SSD controller, utilizes the single / dual-port SSD signal identification signal on the U.2 interface, and realizes the automatic switching of the clock signal and reset signal of the on-chip PCIe PHY0 and PCIe PHY1 of the SSD controller in the single-port and dual-port modes through the PCIe Clock Buffer, 2:1 PCIe Clock Muxer, and 2:1 Single Muxer of the peripheral hardware circuit; realizes the automatic switching of the 4 lanes in the on-chip PCIe PHY0 and the 2 lanes in the on-chip PCIe PHY1 of the SSD controller in the single-port and dual-port modes through the 1:2 PCIe Single Demuxer and 2:1 PCIe Single Muxer of the peripheral hardware circuit, that is, in the single-port mode, the 4 lanes in the PCIe PHY0 are used to combine into 1 port; in the dual-port mode, the 2 lanes in the PCIe PHY0 and the 2 lanes in the PCIe PHY1 are used to combine into 2 ports. Through the hardware circuit and device proposed in this embodiment, single-port and dual-port SSD adaptive design can be implemented.

[0143] In some optional embodiments, the port switching circuit further includes: a plurality of signal connectors and a backplane, wherein a first end of the mode recognition circuit is connected to a bus interface of an external device via a signal connector, and the mode recognition circuit and the signal connector are both fixed to the backplane.

[0144] In this embodiment, a controller for a solid-state hard disk is provided, comprising: the above embodiment and any optional implementation manner thereof including a port switching circuit and a controller body, wherein the controller body includes a first bus interface and a second bus interface, and the first bus interface and the second bus interface are connected to an external device through the port switching circuit.

[0145] In this embodiment, a solid state drive is provided, comprising: the solid state drive controller and the solid state drive body of the above embodiment.

[0146] In this embodiment, a storage product is provided, including: a solid state drive of the above embodiment and a plurality of central processing units, wherein: A first end of the pattern recognition circuit is connected to a bus interface of the CPU, a second end of the pattern recognition circuit is connected to a first end of the gating circuit; a second end of the gating circuit is connected to each bus interface of the storage device; When the pattern recognition circuit recognizes that only one central processor is connected, the pattern recognition circuit outputs a single-port signal to the gating circuit, and the single-port signal is used to control the gating circuit to send the control signal sent by the central processor to each bus interface, and to control the gating circuit to realize the data transmission connection between the central processor and any or designated bus interface; When the pattern recognition circuit recognizes that multiple CPUs are connected, the pattern recognition circuit outputs a multi-port signal to the selection circuit, and the multi-port signal is used to control the selection circuit to transmit control signals and data between a CPU and a corresponding bus interface.

[0147] This embodiment provides a server, including: the solid state hard disk of the above embodiment.

[0148] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A port switching circuit, characterized in that: The port switching circuit is used to realize signal and data transmission between the external device and the storage device. The port switching circuit includes: a mode recognition circuit and a gating circuit, wherein: The first end of the mode recognition circuit is connected to the bus interface of the external device, and the second end of the mode recognition circuit is connected to the first end of the gating circuit; The second end of the gating circuit is connected to each bus interface of the storage device; When the mode recognition circuit recognizes that only one external device is connected, the mode recognition circuit outputs a single-port signal to the gating circuit, and the single-port signal is used to control the gating circuit to send the control signal sent by the external device to each bus interface, and control the gating circuit to realize the data transmission connection between the external device and any one or designated bus interface; When the mode recognition circuit recognizes that multiple external devices are connected, the mode recognition circuit outputs a multi-port signal to the selection circuit, and the multi-port signal is used to control the selection circuit to transmit control signals and data between an external device and a corresponding bus interface.

2. The port switching circuit according to claim 1, characterized in that: The control signal includes: a reset signal and a clock signal, wherein: The gating circuit sends the reset signal and the clock signal sent by the external device to each of the bus interfaces based on the single port signal, and each of the bus interfaces multiplexes the reset signal and the clock signal; The gating circuit sends the reset signal and the clock signal sent by each external device to a corresponding bus interface based on the multi-port signal.

3. The port switching circuit according to claim 2, characterized in that: The storage device is a controller of a solid-state hard disk, the controller of the solid-state hard disk includes a first bus interface and a second bus interface, the bus interface of the first bus interface includes four data interfaces, a clock signal interface, and a reset signal interface, the bus interface of the second bus interface includes two data interfaces, a clock signal interface, and a reset signal interface, the mode recognition circuit includes: a U.2 interface connector, wherein, The U.2 interface connector includes a first clock signal interface, a second clock signal interface, a first reset signal interface, a second reset signal interface, an enable output interface, and four data interfaces; The first end of the first clock signal interface and the first end of the first reset signal interface are connected to the clock signal interface and the reset clock signal interface of the first external device respectively, and the second end of the first clock signal interface and the second end of the first reset signal interface are connected to the first end of the gating circuit; The first end of the second clock signal interface and the first end of the second reset signal interface are respectively used to connect to the clock signal interface and the reset clock signal interface of the second external device, and the second end of the second clock signal interface and the second end of the second reset signal interface are connected to the first end of the selection circuit.

4. The port switching circuit according to claim 3, characterized in that: The gating circuit includes: a signal line switching circuit and a data line switching circuit, wherein: The first end of the signal line switching circuit is connected to each clock signal interface, each reset signal interface, and enable output interface of the U.2 interface connector, and the second end of the signal line switching circuit is connected to each bus interface; the signal line switching circuit sends the clock signal and the reset signal to each bus interface based on the single-port signal; the signal line switching circuit transmits the clock signal and the reset signal sent by the first external device to the first bus interface, and transmits the clock signal and the reset signal sent by the second external device to the second bus interface based on the multi-port signal; The first end of the data circuit switching circuit is connected to each data interface and enable output interface of the U.2 interface connector, and the second end of the data circuit switching circuit is connected to each data interface of each bus interface; when the single-port signal is received, the data circuit switching circuit realizes data transmission between the external device and the first bus interface; when the multi-port signal is received, the data circuit switching circuit realizes data transmission between the first external device and the first bus interface, and data transmission between the second external device and the second bus interface.

5. The port switching circuit according to claim 4, characterized in that: The signal line switching circuit includes: a clock signal switching circuit and a reset signal switching circuit, wherein: A first end of the clock signal switching circuit is connected to each clock signal interface of the U.2 interface connector, a second end of the clock signal switching circuit is connected to an enable output end of the U.2 interface connector, and a third end of the clock signal switching circuit is connected to a clock signal interface of each bus interface; When a single-port signal is received, the clock signal switching circuit transmits the clock signal to each bus interface; when a multi-port signal is received, the clock signal switching circuit transmits the clock signal of the first external device to the first bus interface and transmits the clock signal of the second external device to the second bus interface; A first end of the reset signal switching circuit is connected to each reset signal interface of the U.2 interface connector, a second end of the reset signal switching circuit is connected to an enable output end of the U.2 interface connector, and a third end of the reset signal switching circuit is connected to a reset signal interface of each bus interface; When a single-port signal is received, the reset signal switching circuit transmits the reset signal to each bus interface; when a multi-port signal is received, the reset signal switching circuit transmits the reset signal of the first external device to the first bus interface and transmits the reset signal of the second external device to the second bus interface.

6. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a clock buffer and a 2-to-1 clock signal multiplexer, wherein: The first end of the clock buffer is connected to the first clock signal interface of the U.2 interface connector, and the second end of the clock buffer is connected to the third end of the 2-to-1 clock signal multiplexer; The first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

7. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a signal through line and a 2-to-1 clock signal multiplexer, wherein: The first end of the signal direct line is connected to the first clock signal interface of the U.2 interface connector, and the second end of the signal direct line is connected to the third end of the 2-to-1 clock signal multiplexer and the clock signal interface of the first bus interface; The first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

8. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a first clock buffer, a second clock buffer, a first 2-to-1 clock multiplexer, and a second 2-to-1 clock multiplexer, wherein: A first end of the first clock buffer is connected to a first clock signal interface of the U.2 interface connector, a second end of the first clock buffer is connected to a clock signal interface of the first bus interface, and a second end of the first clock buffer is connected to a third end of the second 2-to-1 clock multiplexer; A first end of the first 2-to-1 clock multiplexer is connected to a first clock signal interface of the U.2 interface connector, a second end of the first 2-to-1 clock multiplexer is connected to an enable output interface of the U.2 interface connector, and a fourth end of the first 2-to-1 clock multiplexer is connected to a clock signal interface of the first bus interface; A first end of the second clock buffer is connected to the second clock signal interface of the U.2 interface connector, a second end of the second clock buffer is connected to the clock signal interface of the second bus interface, and a second end of the second clock buffer is connected to a third end of the first 2-to-1 clock multiplexer; A first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface of the U.2 interface connector, a second end of the second 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and a fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface; When the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first clock buffer outputs a homologous clock signal to the first bus interface and the second 2-to-1 clock multiplexer, and the second 2-to-1 clock multiplexer outputs the homologous clock signal to the second bus interface, and the first 2-to-1 clock multiplexer is locked; When the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the second clock buffer outputs a homologous clock signal to the second bus interface and the first 2-to-1 clock multiplexer, the first 2-to-1 clock multiplexer outputs the homologous clock signal to the first bus interface, and the second 2-to-1 clock multiplexer is locked; When the clock signal interface of the first external device and the clock signal interface of the second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer are locked, and the first clock buffer outputs the same source clock signal of the clock signal of the first external device to the first bus interface, and the second clock buffer outputs the same source clock signal of the clock signal of the second external device to the second bus interface.

9. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a first 2-to-1 clock multiplexer and a second 2-to-1 clock multiplexer, wherein: A first end of the first 2-to-1 clock multiplexer is connected to a first clock signal interface connected to the U.2 interface, a second end of the first 2-to-1 clock multiplexer is connected to an enable output interface connected to the U.2 interface, a third end of the first 2-to-1 clock multiplexer is connected to a second clock signal interface connected to the U.2 interface, and a fourth end of the first 2-to-1 clock multiplexer is connected to a clock signal interface of the first bus interface; A first end of the second 2-to-1 clock multiplexer is connected to a second clock signal interface connected to the U.2 interface, a second end of the second 2-to-1 clock multiplexer is connected to an enable output interface connected to the U.2 interface, a third end of the second 2-to-1 clock multiplexer is connected to a first clock signal interface connected to the U.2 interface, and a fourth end of the second 2-to-1 clock multiplexer is connected to a clock signal interface of a second bus interface; When the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; When the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; When the clock signal interface of the first external device and the clock signal interface of the second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the first external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the second external device to the second bus interface.

10. The port switching circuit according to claim 6, characterized in that: The reset signal switching circuit includes: a signal through line and a reset signal multiplexer, wherein: The first end of the signal through line is connected to the first reset signal interface of the U.2 interface connector, and the second end of the signal through line is connected to the reset signal interface of the first bus interface; The first end of the reset signal multiplexer is connected to the second reset signal interface of the U.2 interface connector, the second end of the reset signal multiplexer is connected to the first end of the signal pass-through line, the third end of the reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the reset signal multiplexer is connected to the reset signal interface of the second bus interface.

11. The port switching circuit according to claim 6, characterized in that: The reset signal switching circuit comprises: a first reset signal multiplexer and a second reset signal multiplexer, wherein: The first end and the second end of the first reset signal multiplexer are connected to the first reset signal interface and the second reset signal interface of the U.2 interface connector, the third end of the first reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first reset signal multiplexer is connected to the reset signal interface of the first bus interface; The first end and the second end of the second reset signal multiplexer are connected to the second reset signal interface and the first reset signal interface of the U.2 interface connector, the third end of the second reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second reset signal multiplexer is connected to the reset signal interface of the second bus interface; When the reset signal interface of the external device is connected to the first reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface; When the reset signal interface of the external device is connected to the second reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface; When the reset signal interface of the first external device and the reset signal interface of the second external device are respectively connected to the first reset signal interface and the second reset signal interface connected to the U.2 interface, and the first reset signal multiplexer and the second reset signal multiplexer receive a multi-port signal, the first reset signal multiplexer outputs the reset signal of the first external device to the first bus interface, and the second reset signal multiplexer outputs the reset signal of the second external device to the second bus interface.

12. The port switching circuit according to claim 4, characterized in that: The data line switching circuit comprises: a first data direct line, a second data direct line, a first data line switching sub-circuit, and a second data line switching sub-circuit, wherein: The first data through line connects the first data interface of the U.2 interface connector to the first data interface of the first bus interface; The second data through line connects the second data interface of the U.2 interface connector to the second data interface of the first bus interface; A first end of the first data line switching subcircuit is connected to the third data interface of the U.2 interface connector, a second end of the first data line switching subcircuit is connected to the enable output port of the U.2 interface connector, and a third end of the first data line switching subcircuit is connected to the third data interface of the first bus interface and the first data interface of the second bus interface; The first end of the second data line switching subcircuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second data line switching subcircuit is connected to the enable output port of the U.2 interface connector, and the third end of the second data line switching subcircuit is connected to the fourth data interface of the first bus interface and the second data interface of the second bus interface.

13. The port switching circuit according to claim 12, characterized in that: The first data line switching sub-circuit includes: a first sending switching circuit and a first receiving switching circuit, wherein: A first end of the first transmission switching circuit is connected to the third data interface of the first bus interface, a second end of the first transmission switching circuit is connected to the first data interface of the second bus interface, a third end of the first transmission switching circuit is connected to the third data interface of the U.2 interface connector, and a fourth end of the first transmission switching circuit is connected to the enable output port of the U.2 interface connector; The first end of the first receiving switching circuit is connected to the third data interface of the U.2 interface connector, the second end of the first receiving switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the first receiving switching circuit is connected to the third data interface of the first bus interface, and the fourth end of the first receiving switching circuit is connected to the first data interface of the second bus interface.

14. The port switching circuit according to claim 13, characterized in that: The second data line switching sub-circuit includes: a second sending switching circuit and a second receiving switching circuit, wherein: A first end of the second sending switching circuit is connected to the fourth data interface of the first bus interface, a second end of the second sending switching circuit is connected to the second data interface of the second bus interface, a third end of the second sending switching circuit is connected to the fourth data interface of the U.2 interface connector, and a fourth end of the second sending switching circuit is connected to the enable output port of the U.2 interface connector; A first end of the second receiving switching circuit is connected to the fourth data interface of the U.2 interface connector, a second end of the second receiving switching circuit is connected to the enable output port of the U.2 interface connector, a third end of the second receiving switching circuit is connected to the fourth data interface of the first bus interface, and a fourth end of the second receiving switching circuit is connected to the second data interface of the second bus interface; When the second transmission switching circuit receives a single-port signal, the second transmission switching circuit connects the fourth data interface of the first bus interface to the fourth data interface of the U.2 interface connector; when the second transmission switching circuit receives a multi-port signal, the second transmission switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector; When the second receiving switching circuit receives a single-port signal, the second receiving switching circuit connects the fourth data interface of the second bus interface to the second data interface of the U.2 interface connector; when the second receiving switching circuit receives a multi-port signal, the second receiving switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

15. The port switching circuit according to claim 14, characterized in that: The first transmission switching circuit and the second transmission switching circuit both include: a 2:1 signal multiplexer; The first receiving switching circuit and the second receiving switching circuit both include: a 1:2 signal demultiplexer.

16. The port switching circuit according to claim 1, characterized in that: Also includes: A plurality of signal connectors, wherein the first end of the pattern recognition circuit is connected to a bus interface of an external device through a signal connector.

17. The port switching circuit according to claim 1, characterized in that: Also includes: A backplane, wherein the mode recognition circuit and the signal connector are both fixed to the backplane.

18. The port switching circuit according to claim 1, characterized in that: The clock signal, reset signal, received and sent data of the external device are all differential interfaces and differential data.

19. A controller, characterized in that: The controller is applied to a solid state drive, and the controller includes: the port switching circuit and the controller body as described in any one of claims 1-17, wherein the controller body includes a first bus interface and a second bus interface, and the first bus interface and the second bus interface are connected to an external device through the port switching circuit.

20. A solid state hard disk, characterized in that: include: The solid state drive controller and solid state drive body as described in claim 19.

21. A storage product, characterized in that: include: The solid state drive and multiple central processing units as claimed in claim 20, wherein: A first end of the pattern recognition circuit is connected to a bus interface of the CPU, a second end of the pattern recognition circuit is connected to a first end of the gating circuit; a second end of the gating circuit is connected to each bus interface of the storage device; When the mode recognition circuit recognizes that only one central processor is connected, the mode recognition circuit outputs a single-port signal to the gating circuit, and the single-port signal is used to control the gating circuit to send the control signal sent by the central processor to each bus interface, and control the gating circuit to realize the data transmission connection between the central processor and any one or designated bus interface; When the pattern recognition circuit recognizes that multiple central processing units are connected, the pattern recognition circuit outputs a multi-port signal to the selection circuit, and the multi-port signal is used to control the selection circuit to transmit control signals and data between a central processing unit and a corresponding bus interface.

22. A server, characterized in that: include: The solid state drive of claim 20.

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