60 results about "Data bus inversion" patented technology

A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.

A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.

A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.

Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.