16 results about "Data bus inversion" patented technology

Aspects of a storage device including a memory and a controller are provided, which allow for error detection or data integrity checking during data transfer of write operations and read operations. The controller may be configured to generate data integrity information based on at least one data byte to be written to the memory, and to transfer the at least one data byte contemporaneously with the data integrity information on separate data paths to the memory. The controller may be configured to select between transferring data bus inversion information or the data integrity information based on whether a data integrity protection mode is active between the memory and the controller. The memory may be configured to receive the at least one data byte and the data integrity information from the controller, and detect whether an error exists in the at least one data byte based on the data integrity information.

Disclosed herein is transmission and reception scheme for communicating data over a data bus and determining errors in the communicated data. The system includes a transmitter circuitry and a receiver circuitry. The transmitter circuitry generates a CRC code based on an input data word, encodes the input data word with a data-bus inversion (DBI) vector, and transmits the DBI-encoded data word along with the CRC code to the receiver circuitry. The receiver circuitry decodes, over a plurality of candidate DBI vectors, the DBI-encoded data word based on each candidate DBI vector, computes an associated CRC value for each candidate data word, and determines a reconstructed input data word based on which associated CRC value of the plurality of candidate data words matches the CRC code.

The invention relates to a DDR read data training method and device, equipment and a storage medium. The method comprises the steps that a first target pin corresponding to a data bus inversion line is determined from first mapping information, the first mapping information is used for representing the mapping relation of physical wiring between a pin on a controller and a DDR, and the physical wiring comprises the data bus inversion line and a plurality of data lines; replacing a data bus inversion line corresponding to the first target pin in the first mapping information with a target data line to obtain second mapping information; according to the second mapping information, a first target signal sent by a DDR corresponding to a second target pin is obtained, and the second target pin is a pin corresponding to the target data line logic; and performing read data training according to the first target signal. By adopting the method, the hardware resource consumption can be reduced during data reading training.

The present disclosure is directed to a method for data bus inversion. The method includes determining a first metric associated with transitioning a data bus from carrying a first binary string to carrying a second binary string. The method includes determining a second metric associated with transitioning the data bus from carrying the first binary string to carrying a complement of the second binary string. The method includes transitioning the data bus from carrying the first binary string to carrying the second binary string or the complement of the second binary string based on the first metric and the second metric.

Memory devices, electronic devices, and methods of storing data are provided. The electronic device includes a host configured to output data and a memory device including a memory storage device configured to receive and store the data. The host is configured to generate data bus inversion (DBI) information about the data to be provided to the memory device according to a data parallelization system internal to the memory device and provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage device, the data being output from the host, the data being encoded according to the DBI information, the data being provided according to the data parallelization system.

A data encoding scheme for transmission of data from one circuit to another circuit combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used. The data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data is transmitted from one circuit to another circuit.

A memory system includes a host and a memory device configured to transmit and receive data to and from the host through a plurality of channels. The host may include an error correction code (ECC) engine configured to generate ECC parity information corresponding to write data to be transmitted to the memory device, a data bus inversion (DBI) engine configured to generate DBI information corresponding to the write data to be transmitted to the memory device, and a memory controller configured to control the ECC engine and the DBI engine. The plurality of channels may include a data channel group, including a plurality of data channels, and an ECC channel group including a plurality of ECC channels. The DBI information may be transmitted from the host to the memory device through an unused ECC channel in the ECC channel group.

A memory device is provided. A memory device comprises a decoder configured to receive first input data that is based on host data and a first data bus inversion (DBI) signal indicating whether the first input data is inverted, and output the host data, a counter configured to count a number of bits with a first value in the first DBI signal, an indicator generation circuit configured to generate an indicator signal based on a first counting value indicative of the number of bits with the first value in the first DBI signal, and a data selection circuit configured to receive the host data and, in response to the indicator signal, select write data to be stored in a memory cell array.

An NRZ / PAM-3 / PAM-4 multi-mode transmitter comprises eight identical data channels and two identical differential feedforward clock channels, the differential feedforward clock channels generate two differential clock signals according to a half-rate differential clock and output to a receiving end, the data channels perform serialization, equalization and DBI encoding processing on a plurality of pseudo-random binary sequences (PRBS) according to a mode control word and a clock signal output by the differential feedforward clock channels, and output the DBI encoded data to the receiving end; through power optimal receiving end termination, clock embedded DBI and multi-mode architecture technology, the ability of low power consumption, high energy efficiency and high bandwidth transmission can be realized.

A system includes first transceivers coupled to data lanes, which are coupled to second transceivers and a first encoder coupled to the first transceivers. The first encoder, responsive to detecting a transmission signal to begin a transmission mode, determines that first bits to be transmitted by the first transceivers over the data lanes include over fifty percent of a first binary value. The first encoder generates a first data-bus-inversion (DBI) polarity signal that alternates in polarity and generates first DBI-encoded bits of the first of bits based on the first DBI polarity signal. The first encoder causes the transmission signal to be transmitted to a second encoder coupled to the second transceivers, the transmission signal to synchronize DBI encoding between the first and second encoders.

A memory device is provided. A memory device includes a decoder configured to receive first input data based on host data and a first data bus inversion (DBI) signal indicating whether the first input data is inverted, and output the host data; a counter configured to count a number of bits having a first value in the first DBI signal; an indicator generation circuit configured to generate an indicator signal based on a first count value indicating a number of bits having a first value in the first DBI signal; and a data selection circuit configured to receive host data and select write data to be stored in the memory cell array in response to the indicator signal.

The embodiment of the present disclosure provides a data bus inversion circuit and a memory, wherein the data bus inversion circuit comprises: a preprocessing circuit configured to receive a comparison result of current data and previous data, and to preprocess the comparison result to output a preprocessing signal; a first comparison circuit configured to receive the preprocessing signal and output a first comparison signal based on the preprocessing signal; the first comparison signal is used to determine whether a number of preset values in the comparison result is greater than or equal to a first value, wherein the preset value represents that corresponding bit data of the current data and the previous data is different; a second comparison circuit configured to receive the preprocessing signal and output a second comparison signal based on the preprocessing signal; the second comparison signal is used to determine whether the number of preset values is greater than or equal to a second value; and a signal processing circuit configured to receive the first comparison signal, the second comparison signal and a data inversion signal corresponding to the previous data, and output a data inversion signal of the current data.

A communication system includes a plurality of simultaneous bidirectional (SBD) transceiver pairs coupled to a plurality of data lanes. An inversion SBD transceiver pair is coupled to a separate data lane. An encoder coupled to a first side of the plurality of SBD transceiver pairs, the encoder to generate data bus inversion (DBI)-encoded bits from a plurality of input bits and cause an inversion signal to be transmitted over the separate data lane. A decoder coupled to a second side of the plurality of SBD transceiver pairs, the decoder comprising a set of inversion circuits to receive the DBI-encoded bits and output decoded data based on the inversion signal received over the separate data lane.

A memory system includes a host (100) and a memory device (200) configured to transmit and receive data to and from the host (100) through a plurality of channels. The host (100) may include an error correction code (ECC) engine configured to generate ECC parity information corresponding to write data to be transmitted to the memory device (200), a data bus inversion (DBI) engine configured to generate DBI information corresponding to the write data to be transmitted to the memory device (200), and a memory controller configured to control the ECC engine and the DBI engine. The plurality of channels may include a data channel group, including a plurality of data channels, and an ECC channel group including a plurality of ECC channels. The DBI information may be transmitted from the host (100) to the memory device (200) through an unused ECC channel in the ECC channel group.

A high-bandwidth memory (HBM) device includes an interface die and a stack of memory dies. Each memory die includes a data bus inversion (DBI) circuit configured to perform DBI operations in response to a read command received from a host device communicably coupled to the HBM device (e.g., as part of a system-in-package). In response to the read command, the memory die is configured to determine whether it responded to the last read command received from the host device (e.g., based on comparing stack identifiers (SIDs) of the read commands). If the SIDs match, the DBI circuit enables DBI AC encoding, and if the SIDs do not match, the DBI circuit enables DBI DC encoding. The DBI-encoded read data (per DBI AC encoding or DBI DC encoding) is provided by the memory die via the interface die over through-silicon vias.

A memory system supporting a multi-channel interface is provided. The memory system includes: a host; and a memory device configured to transmit and receive data to and from a host through the plurality of channels. The host may include: an error correction code (ECC) engine configured to generate ECC parity information corresponding to write data to be transmitted to the memory device; a data bus inversion (DBI) engine configured to generate DBI information corresponding to write data to be transmitted to the memory device; and a memory controller configured to control the ECC engine and the DBI engine. The plurality of channels may include: a data channel group including a plurality of data channels; and an ECC channel group including a plurality of ECC channels. The DBI information may be sent from the host to the memory device through unused ECC channels in the group of ECC channels.