Sense mechanism for microprocessor bus inversion

Abstract

A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

Description

technical field [0001] The present invention relates to the inversion of the data bus line of a kind of logic circuit, particularly a kind of method and device for quickly estimating the state change of a data output bit group, in order to change the state and point out the data according to x86 microprocessor agreement etc. Inverted state of the bus. Background technique [0002] The architecture of the x86 family of microprocessors, such as those made by Intel Corporation, provides a technique for limiting noise on the data bus. Inverting the bus signal at the transition from one bus cycle to another ensures that half or less of the output bus data signals change state in each cycle. The current x86 protocol has -64-bit data bus D[63:0]#, which consists of four 16-bit D[63:48]#, D[47:32]#, D[31:16]# and D [15:0]# composed of groups. A Data Bus Inversion (DBI) bit group indicates the polarity of each data bus data group. More specifically, each data bus inversion in the...

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However, this technique may consume processing time due to the possible cause of an additional frequency delay time

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