68 results about "X86" patented technology

The invention discloses a heterogeneous resource energy-saving optimization scheduling method and system based on computing power perception, and relates to the technical field of modern computing infrastructure, the system comprises a computing power-energy consumption evaluation module, the computing power-energy consumption evaluation module is used for carrying out computing power and energy consumption evaluation on heterogeneous resources, generating and dynamically updating a computing power-energy consumption mapping table, the heterogeneous resources comprise ARM architecture resources, X86 architecture resources and GPU resources. According to the method, the computing power-energy consumption mapping table is generated and updated in real time, so that the scheduling decision is always based on the latest energy efficiency state of the resources, the accuracy of the basic data is ensured, intelligent task classification and dynamic constraint construction are combined, the system can flexibly balance the task performance and the energy consumption target, and particularly, the strategy can be adaptively adjusted for a high-emergency task; the timeliness of key services is guaranteed, the differentiated scheduling strategy serves as an efficient pre-screening mechanism, task requirements and resource architecture characteristics are accurately matched, and the pertinence and efficiency of resource allocation are remarkably improved.

1. Name of the product in this design: Call Center Headset (X86). 2. Purpose of this design: for communication and audio transmission. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The application relates to the technical field of AMD X86 server, and specifically provides a server restart test optimization method, a server restart test optimization system, a terminal and a storage medium, which comprise the following steps: a BMC judges whether a server restart is stuck in a CPU initialization interface based on a potential signal state of a target pin or a communication state with a BIOS; if the server restart is stuck in the CPU initialization interface, the CPU initialization interface is skipped by repeatedly training the target pin or switching a BIOS running state control system. The application can assist in skipping a stuck PSP interface to enter a BIOS system, and the problem of being stuck in the PSP interface in a restart test process is avoided.

The present disclosure provides for a converged compute platform architecture, including a first infrastructure processing unit (IPU)-only configuration and a second configuration wherein the IPU is coupled to a central processing unit, such as an x86 processor. Connectivity between the two configurations may be accomplished with a PCIe switch, or the two configurations may communicate through remote direct memory access (RDMA) techniques. Both configurations may use ML acceleration through a single converged architecture.

The application discloses a general multi-master parallel on-chip bus supporting X86 architecture and belongs to the field of data transmission buses. The general on-chip bus supports parallel data transmission between multiple master processing devices and multiple slave devices, supports IO and memory space access, multiple priority arbitration strategies, multiple waiting states, an on-chip shared address multi-path data (SAMD) topology structure and three-state multiplexing of a bus data external interface, read and write data are multiplexed, and PPGA pin resources are saved. Through testing and simulation, a general IP core is formed, can be applied in different EDA development tools and development environments, has strong generalization, can effectively avoid repeated work, improve work efficiency, and further reduce research and development cost and research and development time.

The application discloses a kind of block storage performance automation test method, system, storage medium based on FIO, it is related to cloud computing and storage performance test technical field, it is applied to the cloud platform environment including management node and multiple test nodes.By running environment deployment script on management node, automatically complete test node IP management, SSH password-free configuration, firewall processing and according to X86 / ARM architecture adaptive deployment FIO;Run test execution script, precheck is carried out to test disk and time synchronization, start FIO service on multiple nodes according to preset task queue, in turn complete the stress test of covering 4K / 32K / 128K / 1M block size and random, order, 7:3 mixed read-write scene;Run result arrangement script, automatically parse FIO log, extract and uniformly output the IOPS, bandwidth and latency index of each scene.The method reduces manual operation while improving the consistency and result reliability of block storage performance test.

The invention discloses an x86SoC array server dual-mode system based on an intranet VLAN closed loop, and relates to the technical field of cross engineering, and the system comprises a VLAN establishment module which is used for executing a configuration instruction, establishing a VLAN, carrying out MAC port binding and private VLAN function operation at the same time, and generating a secure network closed loop with a trusted SoC as the center; the dual-mode generation module is used for inputting the heterogeneous feature vectors into a small neural network, performing cross-node encryption communication and public VLAN access operation, and generating a high-security intranet-open interconnection dual-mode mode; mAC port binding and private VLAN function operation are executed by establishing the VLAN module, a secure network closed loop with the trusted SoC as the center is generated, synchronous construction of a network isolation strategy and a hardware trusted state is achieved, and the effect of hardware identity trusted verification and dynamic secure network cooperative control is achieved.

The invention relates to the technical field of cross-platform software transplantation, in particular to a migration adaptation method for regional numerical weather forecast software. According to the method, through the software adaptation step, the problem of compatibility of an instruction set and a system environment when existing regional numerical weather forecast software migrates from an X86 architecture to an ARM architecture is solved, and native operation of the regional numerical weather forecast software on a domestic platform is achieved; through a containerization packaging step, software and a complete dependency environment thereof are packaged into a standard mirror image, so that one-time construction and deployment at any place are realized, and the problem of deployment complexity in different operating system environments is thoroughly solved; through the verification step, containerized software is operated, strict cross-platform comparison testing is carried out, prediction precision is quantitatively evaluated, service functions are ensured to be complete, results are reliable, and key technical support is provided for autonomous controllable and safe sustainable development of a meteorological core service system.

The invention provides a method for an ultra-high-definition multi-picture system based on an x86 architecture ST2110 standard, and relates to the technical field of broadcast television and professional video and audio processing. The method comprises the following steps: firstly, configuring input parameters of a video data IP stream, an audio data IP stream and an auxiliary data IP stream; configuring multi-picture layout parameters and generating a multi-picture layout; carrying out reduction processing on each video picture and carrying out rendering synthesis according to the multi-picture layout to obtain a synthesized picture; and packaging the synthesized picture into an IP data message conforming to the ST 2110 standard, and sending the IP data message through a network. According to the method, efficient synthesis and IP output of ultra-high-definition multiple pictures are realized on a universal x86 platform, and the method has good real-time performance, flexibility and engineering applicability.

The present application relates to a kind of rule behavior model real-time code generation method based on rule description file, belong to computer generated force technical field, solve the problem that the development, maintenance efficiency and model execution efficiency of model cannot be considered in prior art.The present application utilizes rule modeling tool without manual hard coding, simplifies rule modeling process and improves the maintainability of the rule behavior model obtained, facilitate subsequent development;Specific format rule description file is converted into equivalent hard coded rule behavior model without using rule explanation reasoning engine, improve the execution efficiency of rule behavior model;There is no demand to specific hardware, the code generated complies with C / C++ language specification, as long as there is C / C++ compiler in certain back-end platform (such as x86 / arm etc.), the behavior model code generated can be compiled to speed up, then can be run in the back-end platform, and most of back-end platforms have C / C++ compiler, therefore the present method is widely used.

In order to solve the problem in existing low-level I / O peripheral abstraction method for cloud FPGAs that limits flexibility of cloud FPGAs'resource management and tenant usage, this invention introduces an implementation method and system of an FPGA bare metal server, in which the cloud FPGAs are treated as the first-class computing resources in the same manner of the general x86 host. Without customizing and developing new system component, the complexity of managing cloud FPGAs is reduced. Meanwhile, tenants are allowed to directly apply for, deploy and leverage the FPGA bare metal host in a pay-as-you-go manner without applying for additional general computing resources.

The invention discloses an x86-64 platform-oriented full-pipeline universal Montgomery modular multiplication operation method, which comprises the following steps of: realizing universal Montgomery modular multiplication operation and modular square operation of a 256-bit elliptic curve cryptographic algorithm by utilizing a BMI2 instruction set and an ADX instruction set and combining a pipeline and a multi-emission mechanism of an x86-64 platform through allocating registers and adjusting calculation steps; wherein the general Montgomery modular multiplication operation comprises multiplication operation, the general Montgomery modular square operation comprises square operation, and both the two operations comprise general Montgomery modular reduction operation; the calculation steps of multiplication and square operation are adjusted, so that two addition chains in the operation are executed in parallel; and adjusting the calculation step of the Montgomery module reduction operation, extending the previous round of additive operation of the cycle calculation step in the operation to the next round, and executing the previous round of additive operation and the next round of multiplication operation in parallel. According to the method, the universal Montgomery modular multiplication operation of the x86-64 platform can be realized, and the operation performance is optimized.

The invention discloses an installation method of a multi-architecture operating system, computer equipment, a medium and a product, and the method comprises the steps: loading a unified proxy EFI file as a unique boot entry of all architectures through a cross-architecture boot loader; loading and starting a native EFI boot file embedded in the unified proxy EFI file according to the device architecture of the current computer device; selecting and loading a mirror image file of the multi-architecture operating system in the mirror image file installation medium by utilizing the started native EFI boot file; and completing the operation system installation on the current computer equipment through the unified installation service in the mirror image file and deleting the unified installation service. The invention aims at solving the problems of framework diversification, installation complexity and guide file decentralization in the prior art, realizing EFI guide unified installation, realizing rapid automatic installation of various hardware frameworks such as x86, ARM, Loongson, RISC-V and the like, and improving the universality and efficiency of system deployment.

The utility model discloses a compatible fault detection card circuit. The circuit comprises an IO chip DBU1, an LPC pin DBLPC1 and an ESPI pin DBESPI, wherein the IO chip DBU1 is provided with an LPC multiplexing pin compatible with an LPC low-speed bus and an ESPI multiplexing pin compatible with an ESPI high-speed bus, the LPC pin DBLPC1 is connected to the LPC multiplexing pin, and the ESPI pin DBESPI is connected to the ESPI multiplexing pin. In addition, the circuit also comprises a digital lamp and a 3VSB to 1.8 VSB circuit. According to the utility model, through the unique circuit design, the compatibility of the LPC low-speed bus and the ESPI high-speed bus is realized, the inconvenience caused by the bus technology upgrading to the debugging of a template and the positioning of after-sales repair problems by engineers in the development process of an X86 platform in the PC industry is effectively solved, and the circuit has the advantages of strong compatibility, convenience, high efficiency, cost reduction, complete functions and the like.

The invention provides a virtual resource pool construction method and management method of a cross-instruction-set architecture. According to the method, an OpenStack component is reconstructed to adapt to an ARM architecture, a security environment is constructed by utilizing TrustZone, and unified integration, security isolation and automatic operation and maintenance of X86 / ARM heterogeneous resources are realized based on an Overlay network and an intelligent scheduling algorithm, so that the problems of heterogeneous compatibility, resource scheduling and security management are solved, and the resource utilization rate and the operation and maintenance efficiency are improved.

The invention provides a fuzzy test method and system for a command line of a multi-architecture operating system. The method comprises the following steps: S1, receiving a command line example or a historical seed file and a test parameter input by a user through a graphical interface; s2, automatically identifying a current system hardware architecture and deploying a corresponding fuzzy test tool supporting a QEMU mode and a dependency environment; s3, automatically generating a test seed file based on user input, and calling a fuzzy test tool to execute a test in a QEMU mode; and S4, automatically collecting test results and generating a visual report. According to the method, through full-process imaging and automatic design, the technical threshold of fuzzy testing is remarkably reduced, unified testing of multiple architecture platforms such as X86, ARM and Loongson is supported, a complete testing closed loop from seed generation to result analysis is formed, and the testing efficiency and the vulnerability mining capacity are effectively improved.

This invention belongs to the field of software porting technology, and specifically relates to a software intelligent porting assistance method and system based on the SW processor. It includes: constructing a SW processor-specific feature knowledge base; performing static analysis on the code of the software to be ported and storing it in a vector database to construct a knowledge base vector index, thereby comparing code differences; performing code preprocessing based on the analysis and vector index results, as well as the SW architecture rules and x86 to SW architecture conversion rules in the specific feature knowledge base; identifying the software language and system environment of the software to be ported and compiling it, generating compilation error logs if compilation errors occur; retrieving errors from the compilation logs, and using the SW large model to identify and call repair tools for code modification via function call functionality; this invention solves the problems of poor compatibility, low efficiency, and poor stability of existing tools adapted to this processor.

The application relates to the technical field of bus diagnosis, and discloses an ESPI and LPC bus diagnosis method and device. The method is as follows: the STRAP pin level of a master control chip is configured through a jump cap short circuit state, so that the master control chip enters an LPC bus working mode or an ESPI bus working mode; a target mainboard is connected; an I / O write operation initiated by the target mainboard in a POST self-checking stage is listened to; when a frame start signal is detected, a start field of a bus frame is analyzed and determined as an I / O write operation type; an address field in the bus frame of the I / O write operation type is analyzed and matched with a target listening address; when the address is matched successfully, a POST Code diagnosis code is acquired from the bus frame. The application realizes a dynamic switching mechanism of the LPC and ESPI double bus protocols through hardware jump cap configuration of the STRAP pin, solves the technical problem that a diagnosis card only supports a single bus protocol in the prior art, and enables a single diagnosis card device to be compatible with all X86 platform mainboards.

The invention relates to the technical field of processors, and provides an RISC-V processor architecture, an instruction processing method, a chip and equipment, and the RISC-V processor architecture comprises a decoding unit which is used for responding to starting of a compatible X86 full-storage-order memory mode, and decoding an input memory access instruction into a microoperation with a corresponding memory order constraint; and the execution unit comprises a loading storage unit, and the loading storage unit is used for executing the microoperation in a manner consistent with the X86 full storage sequence model through hardware sequence control logic. According to the embodiment of the invention, the influence on the execution performance of the RISC-V processor when the multi-thread concurrent program written based on the x86 architecture runs on the RISC-V processor can be reduced or avoided.

This invention relates to the field of autonomous driving control, and discloses a power-down control method, an autonomous driving system, a device, and a storage medium. The method includes: determining the operating state based on the current vehicle data of the autonomous vehicle, determining the module to be powered down based on the operating state, generating a corresponding power-down command, sending the power-down command to the module to be powered down, generating a power-off signal based on the state of the module to be powered down, shutting down the power supply to the module based on the power-off signal, updating the power supply connection of the power management device, and shutting down the power supply of the control device. Based on the characteristic requirements of the onboard autonomous driving computing unit, this invention controls the power state of different modules at different times through an MCU triggered by an ignition shutdown signal, and associates the timing requirements of each ARM module and x86 module through the MCU, thus satisfying the power-down timing and functional requirements of the entire autonomous driving system and improving power-down control efficiency.

The application relates to a multi-architecture industrial control software reverse analysis method based on a machine language large model. The method comprises the following steps: acquiring machine language codes of industrial control software of ARM architecture and x86 architecture, and converting the machine language codes into unified intermediate representations; encoding instruction sequences of the unified intermediate representations by using a Transformer-based encoder to obtain sequence representations of functions; training a model through a contrast learning framework to enhance semantic representation capabilities of the sequence representations, and realizing function function identification of the machine language codes of the industrial control software based on the enhanced semantic representations; constructing a control flow graph of the functions, processing the control flow graph by using a graph neural network to obtain graph representations of the functions; fusing the sequence representations and the graph representations to form fusion representations of the functions, and performing code similarity matching based on the fusion representations. The method improves semantic understanding accuracy in industrial control software vulnerability mining, cross-platform migration and other scenes.

The application discloses an active identification carrier based on a RISC-V architecture, which comprises a baseband chip, a radio frequency chip and a storage chip; the baseband chip adopts the RISC-V architecture, and the baseband chip comprises a main function module and an extended function module; the main function module comprises a CPU processor, a codec and a digital signal processor; the extended function module is used for carrying industrial identification and a key; the radio frequency chip is used for signal transmission and reception; and the storage chip is used for data storage. The application has the advantages and beneficial effects that the advantages of the light, simple architecture of the RISC-V instruction set are fully utilized, the processing speed is increased, different parts can be organized together in a modular way, different identification application scenarios can be met through a unified architecture, and common x86 and ARM cannot realize the same.

The invention discloses a kubernetes container cloud X86 and ARM architecture hybrid rapid deployment method, equipment and a medium, belongs to the technical field of software deployment, and aims to solve the technical problem of how to realize kubernetes container cloud X86 and ARM architecture hybrid rapid deployment, reduce development and operation and maintenance cost and improve the development efficiency. According to the technical scheme, the method comprises the following steps: directly deploying a jar package generated by compiling based on an X86 server and an ARM server to a container cloud, and no longer compiling a Dockerfile to construct a mirror image; the method specifically comprises the following steps: compiling a latest code to generate an application package; the method comprises the following steps: providing an X86 and ARM operating system basic mirror image containing a program running environment; uploading the application packet to the FTP according to the service requirement; the application package runs in the Pod, and the Pod is provided with one or more Init containers which are started earlier than the application container.

The invention discloses a multi-dimensional data visualization management system based on an intelligent computing platform. The multi-dimensional data visualization management system comprises a cross-platform data interaction layer, a multi-scene visualization engine layer, a dynamic adaptation layer, a user interaction layer and a deployment operation and maintenance layer. According to the invention, by constructing a multi-scene visual template library and supporting dynamic adaptation of business scenes and development of user-defined components, visual full coverage of multiple scenes such as intelligent computing platform AI training and commercial computing power leasing is realized; by means of multi-protocol adaptation, heterogeneous hardware recognition and containerization deployment technologies, binding limitation of an x86 architecture, a Linux system and a Slurm scheduling system is broken through, and flexible adaptation and deployment across hardware, systems and cloud environments are supported; and meanwhile, a scene-based interface customization function, a template reuse function and an exclusive component development function are provided, so that personalized monitoring requirements of different intelligent calculation services are effectively met, and technical pain points of an existing system are comprehensively solved.

The application provides a protein-ligand affinity evaluation method based on a domestic supercomputing platform, comprising: a domestic supercomputing production environment building step comprising: compiling dependent libraries required for running a deep learning model, and completing framework configuration of SWPyTorch; a deep learning model design and implementation step comprising: constructing a deep learning model based on a protein-ligand affinity evaluation dataset, implementing the deep learning model based on a PyTorch framework under an X86 platform, after model implementation, model transplantation, and transplantation of the deep learning model to the domestic supercomputing platform; a deep learning model parallel optimization step comprising: based on the domestic supercomputing platform, optimizing the deep learning model from data parallelism, calculation parallelism, communication parallelism, operator library optimization, and SWPyTorch multi-node parallelism; and a job submission and running step comprising: configuring computing node resources of the domestic supercomputing platform, activating a dependent environment of the domestic supercomputing platform, and submitting a running job.

This disclosure provides a method, apparatus, storage medium, and program product for generating instruction set test cases. The method includes: acquiring a multi-source instruction set of a target project; performing feature cross-matching on the multi-source instruction set to filter out standardized instructions adapted to the target project and construct an instruction list; traversing the instruction list and generating complete test cases based on the instruction features of the currently traversed standardized instructions; and acquiring a complete test case set after the instruction list has been traversed. This method achieves accurate generation and efficient coverage of x86 instruction set test cases by establishing associations between the multi-source instruction features of the target project.

The application discloses a virtual machine vcpu thread special-purpose scheduler based on a linux kernel and KVM, and the main body is VMSCH, characterized in that: the VMSCH is a virtual machine vcpu scheduler, the VMSCH priority is between an RT scheduling strategy and a CFS scheduling strategy, the priority is 99, and the RT priority is adjusted from 1-99 to 1-98, the VMSCH only manages the scheduling of vcpu threads and does not manage other threads. In the application, the duty cycle of vcpu exclusive pcpu can be dynamically configured, and it is unnecessary to configure at booting, so that the flexibility of the scheme of isolating pcpu for vcpu use by using isolate is avoided, pcpu resource waste caused by bandwidth limitation and idle state of the RT scheduling strategy is avoided, and the application has CPU architecture independence, and after implementation, any CPU architecture, such as X86, ARM and Loongson, can be naturally supported, so that the application has extremely wide application range.

The invention provides a method for native compilation and deployment of a time sequence interference radar processing tool chain ISCE2 and MintPy on a domestic ARM architecture. Aiming at three bottlenecks of poor compilation compatibility, difficulty in dependency library collaboration and huge virtualization computing power loss faced by migration from x86 to ARM architecture, the method eliminates nonstandard path hard coding errors through a dynamic path repair mechanism, establishes a hybrid dependency scheduling system, solves symbol conflicts and ABI incompatibility, and deeply optimizes an instruction set to realize performance maximization. Through strict verification, the compiling success rate is remarkably improved to 100% from less than 50%, the computing power utilization rate reaches 100%, the global first set of full-function ARM time sequence InSAR processing system is successfully constructed, and the performance approaches or even exceeds that of an x86 platform under the same hardware scale. The method is completely based on an open source scientific calculation library, the commercial authorization cost is avoided, a full-stack localization technical chain from a chip, an operating system to application software is realized, and important localization technical support and diversified selection are provided for satellite remote sensing deformation monitoring and geological disaster early warning.

The invention provides a method of an ultra-high-definition IP multimode gateway system based on an x86 architecture ST2110 standard, and relates to the technical field of broadcast television and professional audio and video transmission. By configuring ST 2110 IP stream input and output parameters, bidirectional conversion between SDI signals and video, audio and auxiliary data IP streams is realized. According to the method, separation, packaging and parameter matching are carried out on the SDI data, audio and video time sequence synchronization is carried out, and then output is carried out, so that the flexibility and stability of media transmission and the multiplexing capability of existing IT infrastructures are effectively improved.

This invention relates to the field of SIMD technology on the Shenwei platform, and particularly to a method for implementing SIMD intrinsics based on the Shenwei platform. The method includes the following steps: S1: Scan the source code to determine if there are x86 intrinsic functions; S2: Determine if the x86 intrinsic functions can be reconstructed on the Shenwei platform; S3: Reconstruct the x86 intrinsic functions; S4: Perform testing; Test the x86 intrinsic functions reconstructed on the Shenwei platform in step S3 using libjpeg test cases. If the test results on the Shenwei platform are consistent with the test results on the x86 platform, it proves that the SIMD intrinsic functions on the Shenwei platform and the x86 intrinsic functions have the same functionality. This method can achieve x86 intrinsic compatibility at the source code level.