100 results about "X86" patented technology

The invention discloses a heterogeneous resource energy-saving optimization scheduling method and system based on computing power perception, and relates to the technical field of modern computing infrastructure, the system comprises a computing power-energy consumption evaluation module, the computing power-energy consumption evaluation module is used for carrying out computing power and energy consumption evaluation on heterogeneous resources, generating and dynamically updating a computing power-energy consumption mapping table, the heterogeneous resources comprise ARM architecture resources, X86 architecture resources and GPU resources. According to the method, the computing power-energy consumption mapping table is generated and updated in real time, so that the scheduling decision is always based on the latest energy efficiency state of the resources, the accuracy of the basic data is ensured, intelligent task classification and dynamic constraint construction are combined, the system can flexibly balance the task performance and the energy consumption target, and particularly, the strategy can be adaptively adjusted for a high-emergency task; the timeliness of key services is guaranteed, the differentiated scheduling strategy serves as an efficient pre-screening mechanism, task requirements and resource architecture characteristics are accurately matched, and the pertinence and efficiency of resource allocation are remarkably improved.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

1. Name of the product in this design: Call Center Headset (X86). 2. Purpose of this design: for communication and audio transmission. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The invention relates to the technical field of embedded system software development and continuous integration, in particular to a docker-based AGV (automatic guided vehicle) cross compiling method, which comprises the following steps of: constructing an ARM (advanced RISC machines) root file system on an x86 development host by using a virtualization tool, configuring a header file and a dependency library, and packaging and compressing to obtain an ARM root file system mirror image; pulling the basic mirror image from the public warehouse to create an x86 Docker container, copying the ARM mirror image to a specific path of the container and mounting the ARM mirror image to prepare a Docker mirror image special for AGV cross compiling; writing a CMake cross tool chain file in the container, introducing an ARM mounting path, setting a dependency path and appointing a tool chain; then integrating the commands, automatically updating the container through mirror image ID comparison, and constructing operation commands such as Makefile packaging and compiling and the like at the same time; and finally, calling an integration command to start cross compiling, and generating a program capable of running on an ARM board card of the AGV. According to the method, unified and efficient multiplexing of the AGV cross compiling environment can be realized, the development efficiency is improved, the maintenance cost is reduced, and the method is adaptive to an AGV project needing cross compiling.

The application provides an optimization method applied to X86 vector instruction translation, which is used for eliminating redundant instructions generated in the X86 vector instruction translation process, and the method comprises the following steps: obtaining the to-be-optimized code containing multiple instructions after translation processing, and performing the following steps: a mask optimization step: deleting redundant mask register setting instructions in the to-be-optimized code according to preset mask optimization rules to obtain mask optimization code; a vsetvli optimization step: deleting all csrr instructions and redundant vsetvli instructions in the mask optimization code according to preset instruction optimization rules to obtain target optimization code. The technical scheme of the application solves the problem of redundant instructions generated in the X86 vector instruction translation process through mask optimization and vsetvli optimization.

The application relates to the technical field of AMD X86 server, and specifically provides a server restart test optimization method, a server restart test optimization system, a terminal and a storage medium, which comprise the following steps: a BMC judges whether a server restart is stuck in a CPU initialization interface based on a potential signal state of a target pin or a communication state with a BIOS; if the server restart is stuck in the CPU initialization interface, the CPU initialization interface is skipped by repeatedly training the target pin or switching a BIOS running state control system. The application can assist in skipping a stuck PSP interface to enter a BIOS system, and the problem of being stuck in the PSP interface in a restart test process is avoided.

The disclosure provides a low-code informatization system and method and an ARM server, relates to the field of cloud services, and particularly relates to the field of ARM chips. A specific implementation scheme is as follows: the ARM server comprises at least one ARM board card, each ARM board card is deployed with a cloud platform, a technical component, a business middle station and an application front desk; a firewall is connected with the ARM server and is deployed with at least one security service product; and a user equipment accesses the ARM server through the firewall and is deployed with a low-code development tool. The implementation manner not only meets the demand of informatization construction for server computing power, but also greatly reduces the use cost and saves storage space compared with a server based on an X86 architecture under the condition of the same effect, and one-stop delivery of a traditional industry informatization system is realized.

The present invention discloses a processing control system and a control method for PCD tools, and relates to the technical field of tool production. The present invention includes: a power unit including a multi-section robotic arm and connecting parts; the connecting parts are all equipped with servo motors and reducers; the control unit is an X86 general platform, which is used to send operating instructions to the power unit to complete the path tracking and positioning of the robotic arm; the multi-sensor unit includes a laser radar and an ultrasonic probe, which are used to detect and build the robotic arm movement environment and detect the rotation position and speed of the robotic arm; the human-computer interaction unit includes a mouse and a keyboard as an input platform, which is used to input interactive information and control the movement of the robotic arm. The present invention sets the processing parameters of the PCD tool through the human-computer interaction unit, and the control unit positions the robotic arm and the grinding wheel on the robotic arm based on a neural network, and tracks and understands the travel route of the grinding wheel during the welding process in real time, thereby improving the processing efficiency and accuracy of the PCD tool.

The present invention discloses a processor, processing method, and system for automatically selecting the RISC-V or X86 instruction set during the initialization phase. The processor includes an instruction stream detection module and a decoding configuration module. The decoding configuration module includes a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit. The instruction stream detection module is configured to extract an instruction stream, detect and analyze it, and then output a corresponding ISA control signal; the multiplexer is configured to receive the ISA control signal and connect the corresponding decoding circuit accordingly; the ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, the multiplexer connects the X86 decoding circuit; when the instruction stream detection module outputs the second signal, the multiplexer connects the RISC-V decoding circuit. The processor of the present invention can automatically detect instruction stream features and configure corresponding decoding circuits, simplifying the CPU initialization process.

The present disclosure provides for a converged compute platform architecture, including a first infrastructure processing unit (IPU)-only configuration and a second configuration wherein the IPU is coupled to a central processing unit, such as an x86 processor. Connectivity between the two configurations may be accomplished with a PCIe switch, or the two configurations may communicate through remote direct memory access (RDMA) techniques. Both configurations may use ML acceleration through a single converged architecture.

The application discloses a general multi-master parallel on-chip bus supporting X86 architecture and belongs to the field of data transmission buses. The general on-chip bus supports parallel data transmission between multiple master processing devices and multiple slave devices, supports IO and memory space access, multiple priority arbitration strategies, multiple waiting states, an on-chip shared address multi-path data (SAMD) topology structure and three-state multiplexing of a bus data external interface, read and write data are multiplexed, and PPGA pin resources are saved. Through testing and simulation, a general IP core is formed, can be applied in different EDA development tools and development environments, has strong generalization, can effectively avoid repeated work, improve work efficiency, and further reduce research and development cost and research and development time.

The application provides a perspective control method and device suitable for X86 cloud application, the method comprises the following steps: obtaining posture data of a mobile terminal; determining intermediate data according to the posture data, and sending the intermediate data to a cloud server, so that the cloud server determines offset cumulative value offsetY of a height direction and offset cumulative value offsetX of a width direction of a mouse on a cloud application picture of the cloud server according to the intermediate data, and sends the offset cumulative value offsetY and the offset cumulative value offsetX to a system of the cloud server, so as to control the perspective of the X86 cloud application, and the perspective of the X86 cloud application can be controlled.

The application discloses a kind of block storage performance automation test method, system, storage medium based on FIO, it is related to cloud computing and storage performance test technical field, it is applied to the cloud platform environment including management node and multiple test nodes.By running environment deployment script on management node, automatically complete test node IP management, SSH password-free configuration, firewall processing and according to X86 / ARM architecture adaptive deployment FIO;Run test execution script, precheck is carried out to test disk and time synchronization, start FIO service on multiple nodes according to preset task queue, in turn complete the stress test of covering 4K / 32K / 128K / 1M block size and random, order, 7:3 mixed read-write scene;Run result arrangement script, automatically parse FIO log, extract and uniformly output the IOPS, bandwidth and latency index of each scene.The method reduces manual operation while improving the consistency and result reliability of block storage performance test.

The invention discloses an x86SoC array server dual-mode system based on an intranet VLAN closed loop, and relates to the technical field of cross engineering, and the system comprises a VLAN establishment module which is used for executing a configuration instruction, establishing a VLAN, carrying out MAC port binding and private VLAN function operation at the same time, and generating a secure network closed loop with a trusted SoC as the center; the dual-mode generation module is used for inputting the heterogeneous feature vectors into a small neural network, performing cross-node encryption communication and public VLAN access operation, and generating a high-security intranet-open interconnection dual-mode mode; mAC port binding and private VLAN function operation are executed by establishing the VLAN module, a secure network closed loop with the trusted SoC as the center is generated, synchronous construction of a network isolation strategy and a hardware trusted state is achieved, and the effect of hardware identity trusted verification and dynamic secure network cooperative control is achieved.

The utility model provides a control station, and relates to the technical field of equipment testing. The system comprises a master control module, an RS422 discrete module, an interconnection base plate, an X86 computer module, a plurality of Ethernet data acquisition modules and a power supply module. Wherein the main control module is electrically connected with the interconnection base plate through a main control SGMII channel, an interrupt signal link and a main control discrete IO channel; the interrupt signal link is set to be two paths corresponding to a single Ethernet data acquisition module; the RS422 discrete module is used for collecting discrete 422 signals and is internally and electrically connected with the interconnection base plate through a discrete IO channel. The Ethernet data acquisition module is internally and electrically connected with the interconnection base plate through a double-path SGMII channel; the X86 computer module is internally and electrically connected with the interconnection bottom plate through an Ethernet data channel; according to the scheme, the test hardware requirement of the aircraft management system based on the Ethernet bus and adopting a distributed architecture is met.

The invention provides a real-time demodulation method based on satellite communication. The real-time demodulation method specifically comprises the following steps: carrying out downsampling on baseband data; transmitting the down-sampled data to an X86 system through a Pcle bus, and carrying out variable sampling processing; performing physical layer demodulation on the data subjected to variable sampling processing; and carrying out physical layer decoding on the data after the physical layer demodulation. According to the technical scheme, the problems that in the prior art, satellite signals cannot be demodulated in real time, and the demodulation precision is low are solved.

The invention relates to the technical field of cross-platform software transplantation, in particular to a migration adaptation method for regional numerical weather forecast software. According to the method, through the software adaptation step, the problem of compatibility of an instruction set and a system environment when existing regional numerical weather forecast software migrates from an X86 architecture to an ARM architecture is solved, and native operation of the regional numerical weather forecast software on a domestic platform is achieved; through a containerization packaging step, software and a complete dependency environment thereof are packaged into a standard mirror image, so that one-time construction and deployment at any place are realized, and the problem of deployment complexity in different operating system environments is thoroughly solved; through the verification step, containerized software is operated, strict cross-platform comparison testing is carried out, prediction precision is quantitatively evaluated, service functions are ensured to be complete, results are reliable, and key technical support is provided for autonomous controllable and safe sustainable development of a meteorological core service system.

The invention provides a method for an ultra-high-definition multi-picture system based on an x86 architecture ST2110 standard, and relates to the technical field of broadcast television and professional video and audio processing. The method comprises the following steps: firstly, configuring input parameters of a video data IP stream, an audio data IP stream and an auxiliary data IP stream; configuring multi-picture layout parameters and generating a multi-picture layout; carrying out reduction processing on each video picture and carrying out rendering synthesis according to the multi-picture layout to obtain a synthesized picture; and packaging the synthesized picture into an IP data message conforming to the ST 2110 standard, and sending the IP data message through a network. According to the method, efficient synthesis and IP output of ultra-high-definition multiple pictures are realized on a universal x86 platform, and the method has good real-time performance, flexibility and engineering applicability.

The invention discloses a heterogeneous computing power mixed training method and system, and the method comprises the steps: converting a model calculation graph into a universal instruction irrelevant to hardware, packaging the hardware difference of heterogeneous chips GPU, CPU and MLU, and automatically allocating tasks to the optimal hardware according to the operator characteristics; direct communication between the MLU and the GPU is realized through a PCI e P2P direct connection technology, and gradient compression and an asynchronous communication mechanism are combined to reduce transmission delay and hide communication overhead; containerized packaging is carried out on communication libraries and dependencies of x86, ARM and RI SC-V architectures, and assemblies adaptive to an instruction set are integrated, so that cross-architecture one-key deployment and compatibility guarantee are realized; node loads and resource states are collected in real time based on deep reinforcement learning, and the task allocation proportion is dynamically adjusted. According to the method, the efficiency, the stability and the usability of heterogeneous computing power mixed training can be effectively improved.

The present application relates to a kind of rule behavior model real-time code generation method based on rule description file, belong to computer generated force technical field, solve the problem that the development, maintenance efficiency and model execution efficiency of model cannot be considered in prior art.The present application utilizes rule modeling tool without manual hard coding, simplifies rule modeling process and improves the maintainability of the rule behavior model obtained, facilitate subsequent development;Specific format rule description file is converted into equivalent hard coded rule behavior model without using rule explanation reasoning engine, improve the execution efficiency of rule behavior model;There is no demand to specific hardware, the code generated complies with C / C++ language specification, as long as there is C / C++ compiler in certain back-end platform (such as x86 / arm etc.), the behavior model code generated can be compiled to speed up, then can be run in the back-end platform, and most of back-end platforms have C / C++ compiler, therefore the present method is widely used.

The invention discloses an instruction processing method and device based on an X86 instruction set. The method comprises the steps that a processing instruction is received; decoding the processing instruction, and determining that the instruction type of the processing instruction is a scalar instruction or a packaging instruction; obtaining a first source operand and a second source operand corresponding to the processing instruction, inputting the first source operand and the second source operand into an execution unit to execute function operation, and generating initial output; transmitting the initial output to a pipeline-level data fusion unit; if the instruction type is a scalar instruction, replacing all high-order elements in the initial output with high-order elements at corresponding positions in the first source operand; if the instruction type is a packaging instruction, selecting to reserve or replace a corresponding element according to a mask value; and outputting the fused instruction operation result to the target operand. The method is used for achieving scalar instruction high-order data fusion and hardware multiplexing of an AVX512 instruction set mask control channel, and the instruction execution efficiency and the energy consumption efficiency of a processor are improved.

The invention discloses an intelligent integrated disaster recovery method and system, and the method comprises the steps: accessing a device of an X86 architecture and a device of an ARM architecture, and calling a control interface corresponding to each device in a preset heterogeneous device driver library; accessing a computing resource Computeri, a storage resource Storagei and a network resource Networki of each piece of equipment i through the control interface, and constructing a heterogeneous resource pool (ResourcePool); the method comprises the following steps: virtualizing each resource in a resource pool into a standardized resource unit based on a software defined storage and software defined network technology; extracting attribute parameters for each resource unit j to form a resource identification tuple Rj corresponding to the resource unit j, and constructing a uniform resource abstract view table VRDL = [R1, R2, R3,..., Rj,...]; service data synchronization is carried out based on the constructed resources, the service load is monitored for each resource unit j, and the resource load index Wt at the time t is calculated; and when the Wt exceeds a preset threshold value Threshold, triggering a disaster recovery prompt and executing a disaster recovery switching operation by using the VRDL.

This invention discloses a method, apparatus, device, and medium for dynamic library mapping execution in binary translation, comprising: translating and executing the instructions of an x86 executable program; determining whether it is a dynamic library function call instruction; if it is a dynamic library function call instruction, parsing the call instruction to obtain the called function; using the called function as a lookup index key to query a pre-established dynamic library mapping allocator to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining the starting address of the RISC-V dynamic library in memory, and using the first value as an offset value to calculate the absolute address of the function in memory; determining the parameter address of the function based on the second value; performing calculations on the function using the parameter address and the absolute address, and returning the calculation result. This reduces the system overhead during the translation process.

This invention discloses a multifunctional, modular, detachable handheld game console and computing unit based on the x86 architecture. It features high integration, with each component fulfilling its own function, achieving overall strength and a rational functional layout. The left and right controllers are detachable, employing concealed screws to effectively maintain an aesthetically pleasing appearance while facilitating disassembly and maintenance, preventing screws from falling out. Disassembly is simple and convenient, requiring only the snap-fit ​​mechanism. The outer shell is made of profile material with anodizing treatment and detailed CNC machining. While profile material is low-cost and environmentally friendly, it has lower precision and is prone to deformation. Two layers of plastic insulation separate the detachable controller / main unit outer shell modules, preventing heat transfer from the main unit to the controllers and improving the user experience.

The present disclosure relates to an instruction execution method and device and a processor, comprising: identifying whether an instruction to be executed comprises an extended instruction prefix; if yes, extracting a first field for mapping an operation code of the instruction to be executed from the instruction to be executed; judging whether a second field related to a variable length vector register and a third field related to a variable length mask register are extracted from the instruction to be executed according to the first field; if yes, executing the instruction to be executed according to the first field, the second field, the third field, an operation code comprised by the instruction to be executed and an addressing mode field; if not, executing the instruction to be executed according to the first field, the operation code and the addressing mode field. Thus, the portability of software can be improved and the x86 instruction can be easily extended.

The application discloses a method for supporting heterogeneous CPU coexistence in a Qemu simulator, and is based on the following configuration: defining a super CPU type when implementing the simulator, so that the super type definition contains three attributes of X86 CPU, Shenwei AI main core CPU and Shenwei AI slave core CPU, and the corresponding types are defined as SW types; the method comprises the following steps: step 1, registering the CPU types for different types of CPUs; and step 2, initializing the types for different types of CPUs. In the Qemu simulator, the method supports the heterogeneous CPU coexistence of the X86+Shenwei AI heterogeneous model through the heterogeneous CPU type definition and initialization process of the super type, and lays a foundation for realizing the full-system simulation of the X86+AI acceleration card in the same Qemu simulation environment.

In order to solve the problem in existing low-level I / O peripheral abstraction method for cloud FPGAs that limits flexibility of cloud FPGAs'resource management and tenant usage, this invention introduces an implementation method and system of an FPGA bare metal server, in which the cloud FPGAs are treated as the first-class computing resources in the same manner of the general x86 host. Without customizing and developing new system component, the complexity of managing cloud FPGAs is reduced. Meanwhile, tenants are allowed to directly apply for, deploy and leverage the FPGA bare metal host in a pay-as-you-go manner without applying for additional general computing resources.

The invention discloses an x86-64 platform-oriented full-pipeline universal Montgomery modular multiplication operation method, which comprises the following steps of: realizing universal Montgomery modular multiplication operation and modular square operation of a 256-bit elliptic curve cryptographic algorithm by utilizing a BMI2 instruction set and an ADX instruction set and combining a pipeline and a multi-emission mechanism of an x86-64 platform through allocating registers and adjusting calculation steps; wherein the general Montgomery modular multiplication operation comprises multiplication operation, the general Montgomery modular square operation comprises square operation, and both the two operations comprise general Montgomery modular reduction operation; the calculation steps of multiplication and square operation are adjusted, so that two addition chains in the operation are executed in parallel; and adjusting the calculation step of the Montgomery module reduction operation, extending the previous round of additive operation of the cycle calculation step in the operation to the next round, and executing the previous round of additive operation and the next round of multiplication operation in parallel. According to the method, the universal Montgomery modular multiplication operation of the x86-64 platform can be realized, and the operation performance is optimized.

The invention discloses an installation method of a multi-architecture operating system, computer equipment, a medium and a product, and the method comprises the steps: loading a unified proxy EFI file as a unique boot entry of all architectures through a cross-architecture boot loader; loading and starting a native EFI boot file embedded in the unified proxy EFI file according to the device architecture of the current computer device; selecting and loading a mirror image file of the multi-architecture operating system in the mirror image file installation medium by utilizing the started native EFI boot file; and completing the operation system installation on the current computer equipment through the unified installation service in the mirror image file and deleting the unified installation service. The invention aims at solving the problems of framework diversification, installation complexity and guide file decentralization in the prior art, realizing EFI guide unified installation, realizing rapid automatic installation of various hardware frameworks such as x86, ARM, Loongson, RISC-V and the like, and improving the universality and efficiency of system deployment.

The utility model discloses a compatible fault detection card circuit. The circuit comprises an IO chip DBU1, an LPC pin DBLPC1 and an ESPI pin DBESPI, wherein the IO chip DBU1 is provided with an LPC multiplexing pin compatible with an LPC low-speed bus and an ESPI multiplexing pin compatible with an ESPI high-speed bus, the LPC pin DBLPC1 is connected to the LPC multiplexing pin, and the ESPI pin DBESPI is connected to the ESPI multiplexing pin. In addition, the circuit also comprises a digital lamp and a 3VSB to 1.8 VSB circuit. According to the utility model, through the unique circuit design, the compatibility of the LPC low-speed bus and the ESPI high-speed bus is realized, the inconvenience caused by the bus technology upgrading to the debugging of a template and the positioning of after-sales repair problems by engineers in the development process of an X86 platform in the PC industry is effectively solved, and the circuit has the advantages of strong compatibility, convenience, high efficiency, cost reduction, complete functions and the like.