168 results about "X86" patented technology

The invention discloses a prefetch instruction conversion optimization method based on memory access mode virtualization, which comprises the following steps of: when an executable file is executed in a dynamic instruction conversion mode, acquiring an address memory access mode of a prefetch instruction of x86 architecture, and analyzing an operand and an offset calculation mode of the prefetch instruction; according to an address memory access mode, an operand and an offset calculation mode, an instruction or an instruction sequence of an ARM architecture capable of completing memory address calculation and a prefetching function is constructed, a prefetching instruction of an x86 architecture is replaced with a corresponding ARM instruction or instruction sequence to complete instruction dynamic conversion, and conversion of the prefetching instruction of a complex address mode under the x86 architecture is achieved. And the execution reliability of the executable file in the dynamic instruction conversion mode is improved.

The invention relates to a server application architecture migration method and device and a storage medium, and the method comprises the steps that an automatic detection module analyzes and checks a to-be-migrated application under an X86 architecture, and the to-be-migrated application is subjected to static code analysis, dynamic performance analysis and system compatibility check; according to analysis and check results of the automatic detection module, the automatic adjustment module replaces an X86 specific instruction and a library function, performs memory allocation optimization and memory mapping adjustment, and generates an automatic adjustment report; and the automatic optimization module executes a performance benchmark test, and executes memory access optimization, algorithm optimization, task scheduling optimization and multi-core parallelization adjustment according to a test result. According to the server application architecture migration method and device and the storage medium, the architecture adaptation process can be simplified, performance optimization support and automatic dependency relationship management can be provided, the migration efficiency can be improved, and the cost can be reduced.

The invention discloses a memory partition-based dynamic instruction conversion memory access conflict optimization method, which comprises the following steps of: allocating memory sub-regions for each computing core according to a load condition in an ARM (Advanced RISC Machines) many-core system to establish a first mapping relation table; when the executable file is loaded and executed in a dynamic instruction conversion mode, obtaining a second mapping relation table between the thread and the calculation core, and obtaining a thread and a memory address corresponding to a to-be-converted instruction of a memory access instruction class, obtaining a converted first ARM virtual address and a related first address space according to the first mapping relation table and the second mapping relation table, and determining an adjustment mode of the converted instruction according to the relation between the first ARM virtual address and the first address space to complete instruction conversion. The memory access conflict in the dynamic conversion process from the x86 instruction to the ARM instruction on an ARM many-core system is effectively reduced, and the execution performance of a program after dynamic instruction conversion is improved.

The invention discloses an X86 industrial control mainboard identity authentication system based on multi-mode fusion, which relates to the technical field of mainboard identity authentication, and comprises the following steps: acquiring a secret key, generating a dynamic hardware fingerprint by combining cache topology and instruction delay, collecting physical unclonable function characteristics of power supply noise and clock jitter, and generating a circuit fingerprint; generating a firmware execution track, recording dynamic behaviors of a call chain and interrupt processing delay, and constructing a firmware runtime feature library; collecting spatio-temporal characteristics, generating environment fingerprints in combination with a geo-fencing technology, capturing time sequence characteristics, and generating a network behavior portrait in combination with a device topological relation; timestamp synchronization is carried out; simulating a fingerprint data tampering attack; and carrying out weighted fusion on the static features and the dynamic features. The hardware feature acquisition module, the firmware behavior acquisition module and the environment feature acquisition module are arranged, and physical unclonability of circuit fingerprints and time sequence features of firmware behaviors are combined, so that attacks are effectively resisted.

The invention relates to an LLVM-based ST language compiling method and system, and the method comprises the following specific steps: taking an ST source code as input, and decomposing the ST source code into a tag stream token through an application lexical analyzer; constructing an abstract syntax tree AST by using the mark flow token through a syntactic analyzer; filling a global symbol table, and transmitting the global symbol table and the abstract syntax tree to the next stage; performing semantic analysis, including type check, generating an abstract syntax tree with additional semantic information, and transmitting the abstract syntax tree to the next stage; analyzing the abstract syntax tree with the additional semantic information, generating LLVM IR language codes and transmitting the LLVM IR language codes to the next stage; and the LLVM compiler compiles the LLVM IR code after receiving the LLVM IR code, and outputs an X86 target code and a PowerPC target code. According to the method, the transportability and the code generation efficiency of the ST language compiler can be remarkably improved, various target architectures are supported, meanwhile, good expansibility and flexibility are achieved, and complex industrial automation requirements can be met.

The invention discloses a method, a processor and a system for realizing RISC-V architecture to run an X86 instruction set through hardware, and the method comprises the steps: judging whether there is an equivalent RISC-V standard instruction for replacing an X86 instruction, and if there is an equivalent RISC-V standard instruction, determining the X86 instruction and the equivalent RISC-V standard instruction as a first instruction and a second instruction respectively; if the X86 instruction does not exist, whether a non-equivalent RISC-V standard instruction replacing the X86 instruction exists or not is judged, if yes, whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement or not is judged, and if yes, it is determined that the X86 instruction and the non-equivalent RISC-V standard instruction are a third instruction and a fourth instruction respectively; if not, an RISC-V custom instruction replacing the X86 instruction is determined, and the X86 instruction and the RISC-V custom instruction are determined to be a fifth instruction and a sixth instruction respectively; and obtaining an instruction processing result which takes the first or third or fifth instruction as input and correspondingly takes the second or fourth or sixth instruction as output, and storing the instruction processing result in a hardware device. According to the method, the X86 instruction set can be quickly and efficiently operated by the RISC-V architecture.

The invention discloses a heterogeneous resource energy-saving optimization scheduling method and system based on computing power perception, and relates to the technical field of modern computing infrastructure, the system comprises a computing power-energy consumption evaluation module, the computing power-energy consumption evaluation module is used for carrying out computing power and energy consumption evaluation on heterogeneous resources, generating and dynamically updating a computing power-energy consumption mapping table, the heterogeneous resources comprise ARM architecture resources, X86 architecture resources and GPU resources. According to the method, the computing power-energy consumption mapping table is generated and updated in real time, so that the scheduling decision is always based on the latest energy efficiency state of the resources, the accuracy of the basic data is ensured, intelligent task classification and dynamic constraint construction are combined, the system can flexibly balance the task performance and the energy consumption target, and particularly, the strategy can be adaptively adjusted for a high-emergency task; the timeliness of key services is guaranteed, the differentiated scheduling strategy serves as an efficient pre-screening mechanism, task requirements and resource architecture characteristics are accurately matched, and the pertinence and efficiency of resource allocation are remarkably improved.

The invention provides a binary translation system applied to an X86 program, which is used for translating a source program following X86 semantics into a target program following other semantics, and comprises a data acquisition module used for acquiring the source program; the disassembling module is used for dividing a source program into a plurality of basic blocks and analyzing subsequent basic blocks corresponding to each basic block; the backward data flow analysis module is used for sequentially analyzing each instruction in each basic block from back to front so as to obtain a target definition set and a target subsequent use set corresponding to each instruction in the source program; and the translation module is used for eliminating redundant instructions of high-order zero clearing or high-order retention of the general register generated in translation. According to the technical scheme, the register state of the general register corresponding to each instruction of the source program is analyzed through the backward data flow analysis module so as to eliminate redundant instructions generated in the translation process.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

The invention discloses an ARM (Advanced RISC Machines) many-core-oriented x86 instruction conversion data synchronization optimization method, which comprises the following steps of: when a multi-thread executable file is executed in a dynamic instruction conversion mode, constructing a data synchronization optimization module in an ARM many-core system, inserting a synchronization instruction by a program flow analysis unit according to a program flow analysis result, and executing the multi-thread executable file according to the synchronization instruction. A data synchronization window manager inserts a synchronization instruction for a function and a related shared data instruction according to data synchronization related function execution time, and a synchronization instruction combination optimization unit combines the inserted synchronization instruction to realize data synchronization and optimization of an ARM instruction sequence obtained by conversion. According to the method, the performance and the efficiency of data synchronization of the x86 program in the ARM many-core system are improved, the synchronization overhead is reduced, the correctness of program execution and the data consistency are ensured, and an innovative solution is provided for efficient operation of a cross-architecture program.

The invention discloses an instruction stream feature recognition-based instruction conversion memory access conflict optimization method, which comprises the following steps of: in a process of pre-executing an executable file in an ARM (Advanced RISC Machines) many-core system in a dynamic instruction conversion manner, determining shared memories among processes by adopting instruction stream analysis to form a first shared memory list, and on the basis, determining the memory access conflict among the processes; the executable file is loaded and executed again, the memory access type to-be-converted instruction with the memory address located in the first shared memory list is converted into an instruction sequence composed of a locking instruction sequence, a second ARM instruction sequence and an unlocking instruction sequence, and meanwhile conversion execution of the executable file is completed based on a cache consistency protocol. The memory access conflict of the x86 program on the ARM many-core system is obviously reduced, and powerful support is provided for realizing high-performance dynamic instruction conversion.

The present application belongs to the technical field of computers. Provided are an embedded computing module switching circuit, a carrier plate system, and a server. The embedded computing module switching circuit comprises: a first power supply conversion module and a trigger control module, wherein an input end of the first power supply conversion module is electrically connected to a power supply power line, and a power output end of the first power supply conversion module is electrically connected to a power source end of the embedded computing module; a power source end of the trigger control module is electrically connected to a standby power line, a first output end of the trigger control module is electrically connected to a power source control line, and a second output end of the trigger control module is electrically connected to a starting control port of the embedded computing module. By means of the trigger control module, a power source button trigger signal is monitored for and the power supply state of the first power supply conversion module is monitored, such that a power source control signal and a starting control signal can be output, so as to drive the embedded computing module to be started, thereby making a power-on control mode of X86 computers compatible with heterogeneous computing modules.

The invention discloses a floating point instruction conversion calculation precision optimization method based on an extended control word, and the method comprises the steps: calculating a control word through an extended ARM floating point number, and building a rounding mode mapping table, an exception type mapping table and a virtual exception instruction table in advance; the conversion of an x86 floating-point number control word loading instruction is realized based on a rounding mode mapping table and an exception type mapping table, and for an x86 floating-point number calculation instruction, an ARM instruction sequence which the x86 floating-point number calculation instruction should be converted into is preliminarily determined according to whether the x86 floating-point number calculation instruction is a high-precision calculation related instruction or not; the method comprises the following steps of: acquiring an x86 floating-point number calculation instruction, and determining whether to add an instruction group for simulating exception triggering for the x86 floating-point number calculation instruction according to whether the x86 floating-point number calculation instruction exists in a virtual exception instruction list so as to finish conversion of the x86 floating-point number calculation instruction, so that conversion execution from the x86 floating-point number calculation related instruction to an ARM system is realized, the precision loss of program cross-architecture execution is reduced, and the program cross-architecture execution reliability is improved.

The invention discloses a processor, method and system for dynamically switching RISC-V and X86 instruction sets. The processor comprises an instruction reading unit, a translation unit and an instruction processing unit. The instruction reading unit comprises a state machine and a trigger circuit, the instruction reading unit receives an instruction stream and transmits the instruction stream to the state machine, and a target instruction sequence is arranged between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream; the state machine sends a trigger signal to the trigger circuit when receiving the target instruction sequence, otherwise, the trigger signal is not sent; when the trigger circuit receives the trigger signal, the current state of connecting one of the translation unit and the instruction processing unit is switched to the state of connecting the other one of the translation unit and the instruction processing unit; the translation unit is used for translating the X86 instruction sequence into an RISC-V instruction sequence; the instruction processing unit is used for processing the RISC-V instruction sequence. According to the invention, the RISC-V instruction and the X86 instruction can be dynamically switched and processed.

1. Name of the product in this design: Call Center Headset (X86). 2. Purpose of this design: for communication and audio transmission. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The invention relates to the technical field of embedded system software development and continuous integration, in particular to a docker-based AGV (automatic guided vehicle) cross compiling method, which comprises the following steps of: constructing an ARM (advanced RISC machines) root file system on an x86 development host by using a virtualization tool, configuring a header file and a dependency library, and packaging and compressing to obtain an ARM root file system mirror image; pulling the basic mirror image from the public warehouse to create an x86 Docker container, copying the ARM mirror image to a specific path of the container and mounting the ARM mirror image to prepare a Docker mirror image special for AGV cross compiling; writing a CMake cross tool chain file in the container, introducing an ARM mounting path, setting a dependency path and appointing a tool chain; then integrating the commands, automatically updating the container through mirror image ID comparison, and constructing operation commands such as Makefile packaging and compiling and the like at the same time; and finally, calling an integration command to start cross compiling, and generating a program capable of running on an ARM board card of the AGV. According to the method, unified and efficient multiplexing of the AGV cross compiling environment can be realized, the development efficiency is improved, the maintenance cost is reduced, and the method is adaptive to an AGV project needing cross compiling.

The invention discloses an ARM many-core dynamic instruction conversion-oriented exception handling conversion optimization method, which comprises the following steps of: establishing a mapping relation from an x86 exception type to an ARM exception type by constructing an exception type mapping table, and establishing a first ARM exception handling program and a second ARM exception handling program for each ARM exception type; an exception identifier is added to the ARM exception triggering instruction obtained through conversion, when an ARM many-core system is abnormal, it is determined that a first ARM exception handling program or a second ARM exception handling program is started in a multi-core parallel or single thread mode according to the system load and the number of similar exception types, and efficient and accurate exception handling is achieved. The problem of exception handling caused by framework differences is solved, an innovative exception handling conversion solution is provided for cross-framework program conversion, meanwhile, the exception handling efficiency and performance are improved, and the stability and reliability of a system under various conditions are ensured.

The invention discloses a branch instruction conversion optimization method based on a conditional execution mechanism, which comprises the following steps: when an executable file is executed in a dynamic instruction conversion mode, analyzing an x86 architecture branch instruction to determine a front instruction and a jump entry instruction related to the x86 architecture branch instruction, and determining an instruction set required to be executed after jump according to the jump entry instruction; according to the method, the instruction set is set, the instruction conversion mode is determined according to the number of instructions contained in the instruction set, conversion from the x86 architecture branch instruction to the ARM condition execution instruction is completed, performance losses such as processor assembly line refreshing caused by branch jumping of codes after conversion are reduced, and the applicability of a program running on different hardware platforms is expanded.

The invention relates to the field of remote monitoring, and discloses a safety inspection method and system applied to intelligent security, and the method comprises the steps: calculating a potential risk coefficient of a scene element; marking risk nodes of the intelligent security scene, analyzing risk indexes of the risk nodes, defining multi-modal inspection equipment of the risk nodes, and analyzing inspection resistance of the multi-modal inspection equipment to the risk nodes; configuring a mobile inspection device of the risk node, capturing an abnormal behavior of the risk node, locking an abnormal target of the intelligent security scene, analyzing target characteristics of the abnormal target, and constructing a multi-modal tracking path of the multi-modal inspection device and the mobile inspection device; the abnormal development state of the abnormal target is analyzed, when the abnormal development state accords with a preset abnormal development threshold value, the abnormal level of the abnormal target is determined, and abnormal alarm of the intelligent security scene is executed based on the abnormal level. According to the invention, the automatic test efficiency of the X86 tablet interface can be improved.

The application provides an optimization method applied to X86 vector instruction translation, which is used for eliminating redundant instructions generated in the X86 vector instruction translation process, and the method comprises the following steps: obtaining the to-be-optimized code containing multiple instructions after translation processing, and performing the following steps: a mask optimization step: deleting redundant mask register setting instructions in the to-be-optimized code according to preset mask optimization rules to obtain mask optimization code; a vsetvli optimization step: deleting all csrr instructions and redundant vsetvli instructions in the mask optimization code according to preset instruction optimization rules to obtain target optimization code. The technical scheme of the application solves the problem of redundant instructions generated in the X86 vector instruction translation process through mask optimization and vsetvli optimization.

The application relates to the technical field of AMD X86 server, and specifically provides a server restart test optimization method, a server restart test optimization system, a terminal and a storage medium, which comprise the following steps: a BMC judges whether a server restart is stuck in a CPU initialization interface based on a potential signal state of a target pin or a communication state with a BIOS; if the server restart is stuck in the CPU initialization interface, the CPU initialization interface is skipped by repeatedly training the target pin or switching a BIOS running state control system. The application can assist in skipping a stuck PSP interface to enter a BIOS system, and the problem of being stuck in the PSP interface in a restart test process is avoided.

The disclosure provides a low-code informatization system and method and an ARM server, relates to the field of cloud services, and particularly relates to the field of ARM chips. A specific implementation scheme is as follows: the ARM server comprises at least one ARM board card, each ARM board card is deployed with a cloud platform, a technical component, a business middle station and an application front desk; a firewall is connected with the ARM server and is deployed with at least one security service product; and a user equipment accesses the ARM server through the firewall and is deployed with a low-code development tool. The implementation manner not only meets the demand of informatization construction for server computing power, but also greatly reduces the use cost and saves storage space compared with a server based on an X86 architecture under the condition of the same effect, and one-stop delivery of a traditional industry informatization system is realized.

The present invention discloses a processing control system and a control method for PCD tools, and relates to the technical field of tool production. The present invention includes: a power unit including a multi-section robotic arm and connecting parts; the connecting parts are all equipped with servo motors and reducers; the control unit is an X86 general platform, which is used to send operating instructions to the power unit to complete the path tracking and positioning of the robotic arm; the multi-sensor unit includes a laser radar and an ultrasonic probe, which are used to detect and build the robotic arm movement environment and detect the rotation position and speed of the robotic arm; the human-computer interaction unit includes a mouse and a keyboard as an input platform, which is used to input interactive information and control the movement of the robotic arm. The present invention sets the processing parameters of the PCD tool through the human-computer interaction unit, and the control unit positions the robotic arm and the grinding wheel on the robotic arm based on a neural network, and tracks and understands the travel route of the grinding wheel during the welding process in real time, thereby improving the processing efficiency and accuracy of the PCD tool.

The present invention discloses a processor, processing method, and system for automatically selecting the RISC-V or X86 instruction set during the initialization phase. The processor includes an instruction stream detection module and a decoding configuration module. The decoding configuration module includes a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit. The instruction stream detection module is configured to extract an instruction stream, detect and analyze it, and then output a corresponding ISA control signal; the multiplexer is configured to receive the ISA control signal and connect the corresponding decoding circuit accordingly; the ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, the multiplexer connects the X86 decoding circuit; when the instruction stream detection module outputs the second signal, the multiplexer connects the RISC-V decoding circuit. The processor of the present invention can automatically detect instruction stream features and configure corresponding decoding circuits, simplifying the CPU initialization process.

The present disclosure provides for a converged compute platform architecture, including a first infrastructure processing unit (IPU)-only configuration and a second configuration wherein the IPU is coupled to a central processing unit, such as an x86 processor. Connectivity between the two configurations may be accomplished with a PCIe switch, or the two configurations may communicate through remote direct memory access (RDMA) techniques. Both configurations may use ML acceleration through a single converged architecture.

The application discloses a general multi-master parallel on-chip bus supporting X86 architecture and belongs to the field of data transmission buses. The general on-chip bus supports parallel data transmission between multiple master processing devices and multiple slave devices, supports IO and memory space access, multiple priority arbitration strategies, multiple waiting states, an on-chip shared address multi-path data (SAMD) topology structure and three-state multiplexing of a bus data external interface, read and write data are multiplexed, and PPGA pin resources are saved. Through testing and simulation, a general IP core is formed, can be applied in different EDA development tools and development environments, has strong generalization, can effectively avoid repeated work, improve work efficiency, and further reduce research and development cost and research and development time.

The present invention relates to the field of big data analysis, in particular to a Linux printer driver method and system based on a virtual machine across CPU architectures. By using the qemu virtual machine to start at least one minimal Linux environment based on the x86 system architecture, an initial environment is obtained; the Linux printer device located at the usb port is identified and captured based on the virtual machine, the first printer driver is redirected through usb redirection technology, the CUPS service port of the initial environment is mapped by using ip port redirection technology, and the second printer driver is installed on the CUPS service port in the target environment; the content to be printed is obtained, and the printing instruction is executed on the content to be printed based on the target printer driver. The printing tasks can be allocated according to the server CPU, memory, and bandwidth loads, reducing the single point of failure rate.

The application provides a perspective control method and device suitable for X86 cloud application, the method comprises the following steps: obtaining posture data of a mobile terminal; determining intermediate data according to the posture data, and sending the intermediate data to a cloud server, so that the cloud server determines offset cumulative value offsetY of a height direction and offset cumulative value offsetX of a width direction of a mouse on a cloud application picture of the cloud server according to the intermediate data, and sends the offset cumulative value offsetY and the offset cumulative value offsetX to a system of the cloud server, so as to control the perspective of the X86 cloud application, and the perspective of the X86 cloud application can be controlled.

The application discloses a kind of block storage performance automation test method, system, storage medium based on FIO, it is related to cloud computing and storage performance test technical field, it is applied to the cloud platform environment including management node and multiple test nodes.By running environment deployment script on management node, automatically complete test node IP management, SSH password-free configuration, firewall processing and according to X86 / ARM architecture adaptive deployment FIO;Run test execution script, precheck is carried out to test disk and time synchronization, start FIO service on multiple nodes according to preset task queue, in turn complete the stress test of covering 4K / 32K / 128K / 1M block size and random, order, 7:3 mixed read-write scene;Run result arrangement script, automatically parse FIO log, extract and uniformly output the IOPS, bandwidth and latency index of each scene.The method reduces manual operation while improving the consistency and result reliability of block storage performance test.

The invention discloses a method for optimizing calculation precision of floating-point instruction conversion based on extended control words. By extending an ARM floating-point calculation control word, pre-establishing a rounding mode mapping table, an exception type mapping table and a virtual exception instruction table, the conversion of an x86 floating-point control word loading instruction is realized based on the rounding mode mapping table and the exception type mapping table. For an x86 floating-point calculation instruction, the ARM instruction sequence to which the instruction should be converted is preliminarily determined according to whether the instruction is a high-precision calculation-related instruction. Then, according to whether the instruction exists in a virtual exception instruction table, it is determined whether to add an instruction group for simulating exception triggering to the instruction, so as to complete the conversion of the x86 floating-point calculation instruction, realize the conversion and execution of the x86 floating-point calculation-related instruction to the ARM system, reduce the precision loss of program cross-architecture execution, and improve the reliability of program cross-architecture execution.