36 results about "Bus encoding" patented technology

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes encoding data at the EU. The method includes generating control data for decoding the encoded data at the EU. The method includes directing storage of the encoded data in the DRAM. The method includes directing storage of the control data in an on-chip memory separate from the DRAM, wherein the on-chip memory is on a same chip as the EU.

Systems, apparatuses, and methods for reducing the toggle rates on buses are disclosed. A computing system includes a source which provides packets for transmission on a bus. The packet is compressed by a compression engine. The compressed data format of the packet includes locations (bit positions) referred to as holes which do not include valid data. A bus configuration module identifies the locations of the holes and replaces the holes with information from a previous packet transmitted earlier on the bus. The bus configuration module also determines a new transmission bus width for the packet for lowering the bus toggle rate on the bus during transmission.

The invention provides a bus coding sending circuit and method, and a bus transmission system. The circuit includes: a phase sorting unit and a delay processing unit connected in sequence; wherein, the phase sorting unit is used to sort the initial phases of each signal bit in the initial bus signal into the same initial phase; and send the sorted initial phase to the delay processing unit The bus signal; the delay processing unit is used to group each signal bit in the sorted bus signal; and each group of signal bits in the grouped bus signal according to the corresponding delay time The duration is set to be different, and the delay duration corresponding to the first signal bit in each signal bit group is set to the same preset delay mode for delay; and the delayed bus signal is sent to the bus decoding receiving circuit. The present invention avoids the occurrence of the worst crosstalk situation and reduces the transmission delay caused by the crosstalk under the premise that the wiring resource requirement remains unchanged.

The invention provides a comprehensive code based on combined unequal error protection (UEP) with crosstalk avoidance coding (CAC). Aiming at a message packet structure based on a store-and-forward routing policy of network on chip (NoC), by means of regulating the linear dependence of a check matrix (H matrix), an unequal error protection code has capacities of double-bit adjacent error detection (DAED) and single-bit error correction (SEC) for information, and also has a capacity of double-bit error correction for packet heads, thus preferably protecting the important routing information contained in the packet heads. The unequal error protection code is in cascade connection with the CAC at the rear end, thus avoiding transition of a bus with long time delay and high power consumption, thereby preferably improving the influence of the crosstalk on the power consumption and time delay of the bus. According to the invention, based on a unified coding frame, the unequal error protection code is combined with the CAC to obtain the comprehensive code (called an SEC-DAED-selective double adjacent error correction (SDAEC)+ duplicate-add-parity (DAP) code). The comprehensive code has the error control characteristic of the unequal error protection code and the crosstalk avoidance characteristic of the CAC.

The invention relates to a bus on the strengthen Wishbone sheet which leads the bus coding to decrease the bus power consumption. The method in the invention is: first to add the controlling signal BUSENC_O () on the bus main device in Wishbone sheet, as the same, adding the controlling signal BUSENC__I() on the slave device; then to define the meaning in every using bus coding mode of every value from the Wishbone bus data label TGD() and / or address label TGA(); next the main and slave devices arranges the coding mode of the data bus and the address bus used by the communication; last to communicate by the arranging mode. The invention can decrease the bit reversal times of the Wishbone bus to decrease the power consumption in sheet system.

The invention provides a bus coding sending circuit and method, and a bus transmission system. The circuit includes: a sequentially connected phase arrangement unit and a delay processing unit. The phase sorting unit can sort the initial phases of each signal bit in the initial bus signal into the same phase. The delay processing unit groups each signal bit in the sorted bus signal according to the transition direction of each signal bit in the initial bus signal, and obtains at least two signal bit groups and the transition of each signal bit in any signal bit group Grouped bus signals with the same direction, and then perform non-zero delay on all signal bit groups with the same jump direction in the grouped bus signals according to the preset delay method to obtain the delayed bus signal, and send it to the bus decoding receiving circuit Delayed bus signal. The invention eliminates the occurrence of the worst crosstalk and reduces the transmission delay caused by the crosstalk under the premise that the wiring resource requirement remains unchanged.