Data bus system, coder/decoder thereof and coding/decoding method

Abstract

The invention relates to a data bus system and a coder / decoder and a method thereof. The data bus coder comprises: a bus transition coder for carrying out bus transition coding to data according to a preset bus transition coding scheme so as to generate encoding data and transition indicting information; a virtual byte generator for converting the transition indicting information into virtual bytes according to a preset coding mapping; and an error correcting and detecting encoder for generating the error correcting and detecting codes of a virtual character according to a preset error correction and detection coding scheme, wherein the detecting bit number of the preset error correcting and detecting coding scheme is at least one bit more than the error correcting bit number; the mapping leads the hamming distance between all the possible values of the virtual bytes and the referential virtual bytes beyond the conversion of the mapping to be a fixed value and not more than the correcting bit number of the error correcting and detecting coding scheme; and the virtual character contains data to be output, virtual bytes corresponding to the data and stuff bits needing to be allocated with fixed values according to the requirements of the error correcting and detecting coding scheme.

Description

technical field [0001] The invention relates to a computer data bus, in particular to a data bus system based on bus inversion encoding and its encoder, decoder, encoding method and decoding method. Background technique [0002] The rapid development of computer technology, especially the increasing popularity of portable computing applications has prompted people to pay more attention to low-power large-scale integration (VLSI) design. [0003] "Bus-Invert Coding for Low-Power I / O" by Mircea R.Stan and Wayne P.Burleson, IEEE TRANSACTIONS ON VERY LARGE SCALEINTEGRATION (VLSI) SYSTEMS, VOL.3, NO.I, March 1995 discloses a Bus-Invert coding technique for reducing data bus power consumption. [0004] figure 1 The architecture of a data bus system involving a data bus encoder and decoder based on this bus inversion technique is schematically shown. Such as figure 1 As shown, processor 10 accesses memory 40 via data bus 20 and memory controller 30 . When the processor 10 writ...

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