Enhanced wishbone on-chip bus for leading-in bus code

Abstract

The invention relates to a bus on the strengthen Wishbone sheet which leads the bus coding to decrease the bus power consumption. The method in the invention is: first to add the controlling signal BUSENC_O () on the bus main device in Wishbone sheet, as the same, adding the controlling signal BUSENC__I() on the slave device; then to define the meaning in every using bus coding mode of every value from the Wishbone bus data label TGD() and / or address label TGA(); next the main and slave devices arranges the coding mode of the data bus and the address bus used by the communication; last to communicate by the arranging mode. The invention can decrease the bit reversal times of the Wishbone bus to decrease the power consumption in sheet system.

Description

technical field

[0001] The invention relates to an integrated circuit on-chip bus, in particular to a method for introducing bus coding into the Wishbone on-chip bus to reduce bus power consumption. Background technique

[0002] With the rapid development of VLSI, people can integrate millions to hundreds of millions of transistors on a single chip. Such dense integration makes it possible to integrate the functions previously realized by several chips such as processors and peripherals on a small chip, and form a powerful and complete system from a single integrated circuit, which is what is usually called So-called system-on-a-chip. Intellectual property core (IP) multiplexing is one of the core technologies in the SoC era. Because the designs of IP cores vary greatly, they must abide by the same interface standard if they want to be able to connect directly. In a system-on-chip, the processor core and all peripherals are interconnected through a shared bus, so these IP...

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