High performance anti-crosstalk space-time bus coding and decoding method and coding and decoding device thereof

Abstract

The invention discloses a high performance anti-crosstalk space-time bus coding and decoding method and a coding and decoding device thereof, mainly solving the problem that the existing space-time bus coding method has low data transfer efficiency and large bus power consumption. The coding process comprises the following steps: (1) patching a shielding line to divide the N-bit bus to a low bit bus and a high bit bus; (2) separately judging whether the true code and complement code of to-be transmitted data of the two sub-buses to cause worst-case crosstalk or not, generating a marking signal; (3) reaching a conclusion according to the marking signal, if so, inserting N-bit mask words to eliminate the worst-case crosstalk; if worst-case crosstalk does not exists in either of the two sub-buses, selecting a data item which can not cause the worst-case crosstalk in the true code and complement code of to-be transmitted data of the two sub-buses for transmission by the two sub-buses. Themethod of the invention has the advantages of high data transfer efficiency and low power consumption and can be used for the design of the ultra-large scale integrated circuit.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to an on-chip bus of a deep submicron process integrated circuit, in particular to a high-performance anti-crosstalk space-time bus encoding and decoding method and an encoding and decoding device thereof, which can be used in the design of ultra-large-scale integrated circuits. Background technique [0002] With the continuous reduction of the feature size of the integrated circuit process, the size of the integrated device is reduced, and the length of the local interconnect line is shorter, but the length of the global interconnect line still increases with the increase of the chip size. Moreover, due to the reduction of the distance between adjacent interconnect lines and the reduction of the width-to-height ratio of interconnect lines, the coupling capacitance C between interconnect lines I It is close to or even much larger than the ground capacitance C L . The ever-i...

AI Technical Summary

Problems solved by technology

It can be seen that the disadvantages of the above two spatial encoding methods are: a large number of redundant lines need to be added, thereby significantly increasing the redundancy of the chip area

This method can eliminate crosstalk to the greatest extent, but the disadvantage is that it needs to consume more clock cycles to complete a certain amount of data transmission, and introduces more redundant lines and

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