Encoding and decoding method for crosstalk resistant on-chip bus and encoding and decoding device thereof

Abstract

The invention discloses an encoding and decoding method for a crosstalk resistant on-chip bus and an encoding and decoding device thereof, which mainly solve the problems of low data transmission efficiency and high power consumption in the conventional bus encoding method. The method comprises the following steps of: firstly, partitioning an N-position bus into a low-position sub-bus and a high-position sub-bus by inserting a shielded wire; secondly, judging whether a true code and a counter code of data to be transmitted of the two sub-buses can cause worst-case-crosstalk or not and generating a mark signal; and finally, obtaining whether the worst-case-crosstalk exists in the sub-buses or not according to the mark signal, if the worst-case-crosstalk exists in one or both sub-buses, inserting an N-position shielded word to eliminate the worst-case-crosstalk, and if the worst-case-crosstalk does not exist in both sub-buses, optimizing the power consumption of the encoding method, namely, if the true code and the counter code do not cause the worst-case-crosstalk, selecting one with lower power consumption to transmit, and if one code causes the worst-case-crosstalk, selecting the data not causing the worst-case-crosstalk to transmit. The method and the device have the advantages of high data transmission efficiency and low power consumption and can be applied to the design of a super-large scale integrated circuit.

Description

technical field

[0001] The invention belongs to the technical field of microelectronics, and relates to an on-chip bus of deep submicron technology, in particular to an encoding and decoding method and an encoding and decoding device for an anti-crosstalk on-chip bus, which can be used in the design of ultra-large-scale integrated circuits. Background technique

[0002] With the continuous reduction of the feature size of the integrated circuit process, the size of the integrated device is reduced, and the length of the local interconnect line is shorter, but the length of the global interconnect line still increases with the increase of the chip size. Moreover, due to the reduction of the distance between adjacent interconnect lines and the reduction of the width-to-height ratio of interconnect lines, the coupling capacitance C between interconnect lines I It is close to or even much larger than the ground capacitance C L . The ever-increasing coupling capacitance causes ...

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