30results about How to "Reduce latch-up" patented technology

The invention discloses an automatic locking method for a battery replacement station of a flexible direct-current transmission system. The automatic locking method includes the steps of firstly, judging the control mode of the station, the running state of the station and the running states of other stations; secondly, judging the current running state when the flexible direct-current system runs if the station is judged to have the direct-current voltage control mode, the station is in the unlocked state and meanwhile other stations are all in the locked state; thirdly, starting the locking process of the station according to a received system locking control instruction if all the conditions are met, and conducting reactive power reduction control; fourthly, sending a window signal to complete the locking process if the reactive power of the convertor station is zero at present. By means of the automatic locking method, a control and protection system is automatically locked, the locking process of the flexible direct-current transmission system is shortened, impact which is caused by control and protection system incorrect operation generated due to man-made incorrect operation and the like to an alternating-current system is effectively avoided, time consumption of the whole locking process of the flexible direct-current system is lowered, and the complexity in the locking process is lowered.

A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

The invention discloses an automatic locking method for a flexible direct-current transmission system. The automatic locking method includes the following steps of firstly, judging the control mode of a station; secondly, judging the current running state when the flexible direct-current system runs if the station is judged to have the active power control mode; thirdly, starting the locking process of the station according to a received system locking control instruction if all the conditions are met, and conducting power reduction control; fourthly, sending a locking window signal to complete the locking process if both the active power and the reactive power of the current converter station are zero. By means of the automatic locking method for the flexible direct-current transmission system, a control and protection system in a flexible direct-current transmission project is automatically locked, the locking process of the flexible direct-current transmission system is shortened, impact which is caused by control and protection system incorrect operation generated due to man-made incorrect operation and the like to an alternating-current system is effectively avoided, time consumption of the whole locking process of the flexible direct-current system is lowered, the complexity in the locking process is lowered, and running reliability of a direct-current power grid is improved.

The invention provides a cellsovary granulosa cell anti-aging product, and the preparation method and the application of the product. The invention applies cellsovary granulosa cells in preparation of anti-aging products. The cellsovary granulosa cell anti-aging product of the invention is characterized in that in vitro cultivated and amplified cultivation supernatant of female mammalian animal celsovary granulose cells and/or the cell extract is contained; and one or more than one pharmaceutically acceptable medical excipient and antioxidant are contained. Via the cellsovary granulosa cells, the invention is capable of proliferating and secreting large amounts of a plurality of bioactive substances. The invention adopts granulose cells with extremely high bioavailability and similar to female physiological characteristics to cultivate supernatant and the cell extract of the supernatant. The invention can be taken orally, absorbed by skin or be prepared into vaginal suppository to achieve the purpose of anti-aging.

The invention relates to an application of an umbilical cord mesenchymal stem cell conditioned medium, in particular to a protective effect of the human umbilical cord mesenchymal stem cell conditioned medium or freeze-dried powder prepared by the human umbilical cord mesenchymal stem cell conditioned medium on ovarian injury, ovarian senescence and the like.

The invention discloses application of a preparation for regulating and controlling the expression quantity of HSP90B1 in preparation of a medicine for preventing or treating polycystic ovarian syndrome. Through the development of the research, HSP90B1 participates in PCOS ovarian granular cell proliferation, so that the apoptosis of granular cells in follicles is reduced, the imbalance of proliferation and apoptosis is caused, sinus follicle atresia is reduced, and polycystic change and ovulation disorder in ovaries are caused, HSP90B1 possibly participates in the pathologic mechanism of PCOS generation and development, and HSP90B1 is likely to become a drug target of PCOS (polycaprolactone).

The invention relates to the field of semiconductors, in particular to an insulated gate bipolar transistor, an intelligent power device and an electronic product. The insulated gate bipolar transistor comprises a drift region, a gate structure, an emitter, an emitter source region and a body region in contact with the emitter source region, wherein the top layer of the drift region is provided with a first trench and a second trench along the vertical direction of the device, the gate structure is filled in the first trench, the emitter is filled in the second trench, the emitter source region is arranged between the gate structure and the emitter, and the depth of the second trench is greater than the thickness of the emitter source region. A transverse electric field is formed between the gate structure and the emitter metal, the transverse electric field acts on the junction of the emitter source region and the body region to form a carrier collection layer, and the collection andstorage effects of carriers at the junction are enhanced, so that the current between the body region and the emitter source region is reduced, the conduction voltage drop is reduced, and the latch-upeffect occurrence probability is reduced.

The invention discloses an FLIP protein and new applications of encoded genes thereof. The new application of the invention refers to the application of the FLIP protein and the encoded genes thereof in blocking apoptosis induced by FADD and the application in inhibiting apoptosis of ovary granular cells and the application in promoting reproductive performance of animals. The FLIP protein and the encoded genes thereof can obviously inhibit apoptosis of the ovary granular cells induced by FADD, promote growth of oocyte, reduces follicular atresia and serve as potential medicines for improving reproductive performance of cows. The protein and the new applications of the invention provide relatively reliable and concrete experimental basis for increasing ovulation rate of dams and improving reproductive performance thereof, thus enjoying a wide application prospect in improving the reproductive performance of female animals.

The invention discloses a method of manufacturing a semiconductor element. The method comprises the following steps: respectively forming a first stress layer and a second stress layer on a substrate;forming a buffer layer on the first stress layer and the second stress layer; performing an injection manufacturing process on the substrate, to form a precut surface in the substrate on the lower part of the first stress layer and the second stress layer; performing joining treatment, to join a carrier plate on the buffer layer; performing heat treatment, to separate a part of the substrate fromthe precut surface; performing the previous manufacturing process on a precut surface on another part of the substrate.

The invention relates to an MOS (Metal Oxide Semiconductor) type power device which comprises a P-type collector region, an N-type shifting region, a P well, an N-type source region, a first insulating layer, a gate pole, a second insulating layer, an emitting electrode and a collecting electrode, wherein the N-type shifting region is located on the P-type collector region; the P well is selectively formed on the N-type shifting region and has a conduction type which is opposite to the conduction type of the N-type shifting region; the N-type source region is selectively formed on a surface area of the P well; the first insulating layer is located on the N-type shifting region and partially covers the P well; the gate pole is located on the first insulating layer; the second insulating layer covers the gate pole and partially covers the N-type source region; the emitting electrode covers the second insulating layer and is electrically connected with the P well and the N-type source region partially; the collecting electrode is located on the back side of the P-type collector region and is electrically connected with the P-type collector region; a conductive impurity concentration peak area is arranged in the P well; the impurity concentration is gradually reduced from the conductive impurity concentration peak area to the edge of the P well; and a junction bending center of the P well is arranged inside the P well. The invention also provides a manufacturing method of the MOS type power device. The inside resistivity is reduced while the demand on the length of a surface trench is met, thereby reducing the bulk resistor and reducing a latch-up effect.

The invention discloses a manufacturing method of an integrated circuit and the integrated circuit. The manufacturing method comprises the following steps: forming an N-type buried layer on a substrate through ion implantation; forming an epitaxial layer on the N-type buried layer; forming an active region and a passive region in the epitaxial layer; forming a plurality of field oxide layers in the passive region; forming a plurality of low-voltage N-type wells and a plurality of low-voltage P-type wells in the epitaxial layer; forming a plurality of gate structures on the low-voltage N-type well, the low-voltage P-type well and the field oxide layer; and forming a plurality of deep groove isolation structures, wherein the deep groove isolation structures penetrate through the epitaxial layer and the N-type buried layer and extend into the substrate. According to the manufacturing method of the integrated circuit and the integrated circuit, the latch-up effect of the integrated circuit is reduced by adopting a process of a back-end deep groove isolation structure, so that the reliability of the integrated circuit is improved.

The invention relates to an IGBT device with a hole bypass structure and a manufacturing method thereof. A polycrystalline sidewall protection structure, a shallow P+ structure and a P+ deep base region are provided in the active region of the IGBT device; the polycrystalline sidewall protection The structure is located on both sides of the polysilicon gate; the shallow P+ structure is located between the N+ region and the P-base region; the P+ deep base region is set outside the P-base region and surrounds the P-base region to form a hole bypass structure. The invention introduces a highly doped P+ deep base region, improves hole flow distribution, improves electric field distribution, reduces parasitic thyristor latch, and improves IGBT reliability.

The invention discloses an electrostatic protection structure and a forming method thereof, and the structure comprises a substrate which is internally provided with a well region, and the well region comprises a first region, a second region and a third region which are adjacent to each other; the first gate structure and the second gate structure are located on the surface of the second region; the first doped region is located in the second region, and the first doped region, the first gate structure and the second gate structure are electrically connected; the second doped region stretches across the second region and the first region; the third doped region stretches across the second region and the third region, and the third doped region and the first doped region are located on the two sides of the second gate structure respectively; the fourth doped region and the fifth doped region are located in the first region, and the fourth doped region is electrically connected with the fifth doped region; the sixth doped region and the seventh doped region are located in the third region, and the sixth doped region is electrically connected with the seventh doped region. The performance of the electrostatic protection structure is improved.

An integrated circuit that can avoid bolt lock effect. It includes the internal circuit on the base plate with at least one SCR structure; at least one ESD protective groupware and a driving area on the base plate and are coupled a bonding sheet; at least the first shunt diode with a positive pole coupling the bonding sheet and a negative pole coupling a first voltage source; at least a second shunt diode with a negative pole coupling the bonding sheet and a positive pole coupling a second voltage source. The distance between the first and the second shunt diodes and the internal circuit, the distance between the ESD proactive groupware and the driving area is no less than 150 micron; a protective ring to surround the first and the second shunt diodes.