284results about "Color burst signal generation/insertion" patented technology

A synchronization signal detection circuit and method of a digital TV (DTV) receiver are provided. The synchronization signal detection circuit determines a precise main path by determining powers in consideration of the influence of multiple paths near signals located at a peak value location and guarantees a stable operation of an equalizer by using error values output from a decoder to generate a synchronization locking control signal. A power signal based on the correlation of the received signal with a PN511 sequence is filtered to compensate for a dynamic multipath distortion (e.g., due to other multipath signals near signals located at a peak value location). The magnitude of the filtered power signal is then compared (e.g., with a predetermined threshold value) to determine the position of the main path (e.g., at the peak value location, or at a pre or post multipath signal location).

A method for converting a sink device and an apparatus for providing a content using the same are provided. The method for converting the sink device includes receiving a sink device conversion command from a first sink device, transmitting the content to a second sink device if a conversion approval of the sink device is received from the second sink device, and transmitting a control authority related to a content provision from the first sink device to the second sink device.

A single integrated circuit multi-standard demodulator includes an adaptive inverse channel estimator for frequency domain equalization which employs a recursive least square cost function in estimating the inverse channel from the received signal and an error estimate. Utilizing a diagonal correlation matrix, the solution to may be determined utilizing fewer computational resources than required by conventional frequency domain equalizers, shifting from a computational intensive to memory intensive implementation. The memory requirement is fully satisfied by memory available within conventional OFDM decoders, and the necessary computational resources may be readily mapped to the resources available within such decoders, improving integrated circuit cost-effectiveness of the multi-standard demodulator.

The present invention provides encryption techniques useful with digital watermarking payloads. In a first implementation, we encrypt one of two different cooperating watermark payloads, but the encryption and payload data structure helps to authenticate both payloads. Another implementation provides a three encryption key pair system for managing messages and watermark embedding. Still another aspect of the invention is a watermark embedding process that uses encryption to whiten, randomize or spread a message, instead of convention spread-spectrum modulation.

An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides multiple time-base clocks for two transport streams. Transport processor circuitry uses multiple PCRs to track transport streams through decoding, storage and or delivery of the decoded signals for display. Provision of a multiple time-base clock for decoding and delivering multiple transport streams allows display of the two decoded audio-video signals on independent monitors.

A system for monitoring a sporting event includes devices for monitoring characteristics of the event and collecting monitored data. Devices address different aspects of the event and monitor and collect real-time data. The devices process the data into digitized frames, and a digital storage device receives and stores the frames in a random access storage buffer as time-stamped digitized data frames with unique addresses. The storage device is capable of both time-shifting and relational association. The system includes a controller and devices for monitoring and extracting a digitized data frame according to a predetermined criterion. A viewer communicates with the storage device and controller and selects, manipulates, and extracts the digitized data frame. The system records and plays back the monitored data using a circular storage buffer with a memory mapped file and allows playback of stored data without interrupting simultaneous recording of new input data.

A method of synchronising the phase of a local image synchronisation signal generator of a local video data processor in communication with an asynchronous switched packet network to the phase of a reference image synchronisation signal generator of a reference video data processor also coupled to the network, the local and reference processors having respective clocks, the reference and local image synchronisation signal generators generating periodic image synchronisation signals in synchronism with the reference and local clocks respectively comprises the steps of: frequency synchronising the local and reference clocks; the reference video data processor sending, via the network, to the local data processor an image timing packet providing reference image synchronisation data indicating the difference in timing, measured with respect to the reference processor's clock, between the time at which the image timing packet is launched onto the network and the time of production of a reference image synchronisation signal; and the local processor controlling the timing of the production of the local image synchronisation signal in dependence on the reference image synchronisation data and the time of arrival of the timing packet.

A system synchronizes one or more media streams, such as video stream or audio streams, by embedding frame identifiers in each compressed media stream, and then by using synchronizing signals to render each frame simultaneously by referencing the embedded frame identifier. Since the frame identifier is embedded in between encoded frames of the compressed media stream without altering any of the compressed, encoded data, the frame identifier information could be rapidly embedded without creating lag associated with manipulating existing data. This technique could be used, for example, to synchronize a single HD video on a plurality of display devices (e.g. a football game on a wall of video monitors), or to synchronize a plurality of HD video streams on a single display device (e.g. a plurality of live video feeds on a single computer monitor).

An image display device comprising: a display 18 to display an input image and a black image within one frame period; a motion detector 14 to detect a motion information from the input image; a display ratio controller 16 to set a black display time ratio as a ratio of a black period to said one frame period based on the motion information, the black period being a period for displaying the black image within said one frame period; and a display luminance controller 30 to suppress, within a predetermined range, a luminance fluctuation caused by a change in the black display time ratio, the luminance fluctuation corresponding to a fluctuation of a total luminance for said one frame period.

The invention includes a method and apparatus for improving a channel change response time. A method includes propagating a plurality of media streams toward at least one user terminal using a respective plurality of multicast groups and propagating a meta channel toward the at least one user terminal for conveying information adapted for use in selecting one of the media streams in a manner tending to improve the channel change response time. The media streams include an original media stream conveying media content and at least one auxiliary media stream, generated from the original media stream, where each of the at least one auxiliary media stream conveys the media content of the original media stream, where each of the at least one auxiliary media stream is offset in time with respect to the original media stream. The information conveyed by the meta channel is associated with the media streams. A user device may receive the meta channel information and select one of the media streams using the meta channel information in response to a channel change request from the user terminal, or a network device may select one of the media streams for a user terminal in response to a channel change request from the user terminal.

A sync signal generating apparatus and method for video signal processor are disclosed comprising an image processor processing either an input digital television video signal or an input analog television video signal to display one of the signals; a display unit displaying an output signal of the image processor; a frame rate detector detecting a frame of the digital video signal and generating a frame rate signal; a display mode detector detecting whether an image to be currently displayed is a digital television image or an analog television image and generating a display mode signal; a clock generator generating a clock signal according to the display mode signal and the format signal to the image processor; a sync signal compensation unit generating a sync compensation signal based upon the display mode signal, the clock signal, and a vsync signal of the analog television video signal; and a sync signal generator resetting and compensating a sync signal based upon the sync compensation signal and the clock signal and sending the compensated sync signal to the image processor.

The present invention relates to a digital photo album having a hard drive and built-in scanner configured to scan photographic prints. The digital photo album allows a user to save the photographic prints as digital images on the hard drive, or another medium, and then view individual images or play photo album slideshows comprising a plurality of digital images. Additionally, a user may upload digital images from an external medium to the hard drive of the photo album, and then view those images and/or include them in a playlist. The digital photo album of the present invention advantageously allows a user to scan photographic prints, upload or download digital images, and view digital images individually or in an album format, in a substantially automated manner and without the need for complex peripheral devices.

A timing recovery device in a digital television receiver using a VSB system is disclosed. In the present invention, the timing recovery device independently determines whether the detected hsync signal is reliable and operates if the detected hsync signal is reliable.

The present invention provides a method for generating a scenario for a music-and-image-synchronized motion picture comprising the steps of: extracting characteristics of music; extracting structure of the music on the basis of the extracted characteristics of the music and dividing the music into multiple components on the basis of the result of the extraction; analyzing characteristics of images; associating the music and the images with each other according to the characteristics corresponding to the components of the music and the characteristics of the images; and generating a motion picture scenario that enables the associated music and images to be synchronously reproduced. According to the invention, since a component of music and images are associated with each other according to the characteristics of the images, it is possible to synchronously reproduce images that match the contents of music being reproduced, in comparison with the conventional synchronous reproduction.

Disclosed is an imaging system having an imaging device for producing images of objects and picture signals and an imaging controller connected to the imaging device through a transmission line. The imaging device includes a vertical synchronizing signal-producing circuit to produce an internal vertical synchronizing signal for the production of images of objects. The imaging controller includes a delay-measuring circuit and a vertical-synchronization phase-advancing circuit. In the system: the imaging controller transmits a test signal to the imaging device and receives the test signal returned from the imaging device and the delay-measuring circuit measures a delay of a phase of the returned test signal relative to a phase of the original test signal; the vertical-synchronization phase-advancing circuit advances a phase of an external vertical synchronizing signal by the delay and transmits the external vertical synchronizing signal to the imaging device; and the vertical synchronizing signal-producing circuit is reset by a signal transmitted from the vertical-synchronization phase-advancing circuit.

A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.

A video transmission circuit for transmitting video data on a digital serial interface to a receive circuit arranged to process the video data at a constant rate, the circuit including a transmission block comprising: a packet generator arranged to generate, for each image of the video data, a plurality of packets, each containing a pixel group of the image; a transmit circuit arranged to transmit the packets of each image on a digital serial interface at time intervals based on the constant rate; and a synchronization circuit arranged to receive from the receive circuit, after transmission of a plurality of packets, a synchronization signal for synchronizing the beginning of the transmission of a next packet.

In a method of generating a video pixel clock, a frequency of an output video pixel clock is increased to a first frequency setting when a quantity of data read from a frame buffer storing video data is greater than a reference level. The frequency of the output video pixel clock is decreased to a second frequency setting when the quantity of data read from the frame buffer is less than the reference level. Accordingly, an imbalance between frame rates of input and output image signals may be reduced.

A two-stage pixel skew compensation circuit for use with digital display monitors. The first stage of the compensation circuit aligns the edges of the pixels received on the color component signal lines of an analog video signal. The second stage of the de-skew compensation circuit realigns the pixels themselves so that no skew exists between the digitized video color components. The digitized video signals drive a digital video monitor.