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629 results about "Constant rate" patented technology

A constant rate in math is the absence of acceleration. In general, a function with a constant rate is one with a second derivative of 0. If you were to plot the function on standard graph paper, it would be a straight line, as the change in y (or rate) would be constant.

DSL system loading and ordering

Loading and ordering techniques are provided for one-sided and two-sided vectored line groups, as well as loading methodologies that also can be used on a single line, in communication systems such as DSL binders. For single-user lines, bits and energy are optimally allocated for a given set of parameters, which may include maximum rate, minimum rate, maximum margin, target margin, minimum margin and PSD mask of any shape. Iterations, bit-swapping during loading or adaptive margin update during loading can be used in single-user loading, which has low complexity and can be used for a variety of loading objectives and/or goals, such as rate-adaptive, margin-adaptive and fixed-margin objectives. For multi-user vectoring systems, ordering as well as loading is provided for a supplied rate-tuple within a rate region, determining acceptable user loadings and orderings so that the rate-tuple can be implemented. For one-sided vectored DSL, some loading and ordering determines acceptable allocations of bits, energy and decoding/precoding ordering(s) for each tone of each user for a specified set of rates on the vectored lines. PSD determination, ordering and bit allocation can be iteratively used in multi-user loading and ordering and can augment and alter the criteria used for bit swapping procedures used in single lines (or in bonded multiple lines for a single user) so that a favorable vector of rates is achieved for all users. Order swapping can adjust a bit vector and/or rate vector within a constant-rate-sum convex subset of a hyperplane towards the desired vector of user rates for each of the lines.
Owner:ASSIA SPE LLC CO THE CORP TRUST CO

Apparatus and method for friction stir welding using a consumable pin tool

The present invention provides a friction stir welding apparatus operable for welding one or more metals, metal alloys, or other materials. The friction stir welding apparatus includes a pin tool holder, a shoulder having a surface coupled to the pin tool holder, and a pin tool coupled to the pin tool holder, the pin tool at least partially protruding from the surface of the shoulder, wherein the pin tool is made of a consumable pin tool material. Optionally, the shoulder rotates at a predetermined rotational speed and is retractable into/extendable from the pin tool holder at a substantially constant rate. Optionally, the shoulder is also made of a consumable shoulder material that is at least partially incorporated into the volume of a joint to be welded. The consumable shoulder material comprises a material that is the same as, similar to, or dissimilar from one or more materials comprising a workpiece to be friction stir welded. Preferably, the pin tool rotates at a predetermined rotational speed and is retractable into/extendable from the surface of the shoulder at a substantially constant rate. The consumable pin tool material is at least partially incorporated into the volume of the joint to be welded. The consumable pin tool material comprises a material that is the same as, similar to, or dissimilar from one or more materials comprising the workpiece to be friction stir welded.
Owner:GENERAL ELECTRIC CO

Digital pulse-width-modulation generator

A digital pulse-width-modulation (PWM) generator comprising: an n bit digital magnitude comparator having first and second n bit inputs and an output indicative of the relative values of the signals applied at the first and second inputs; a first n bit digital up / down counter having a count direction input coupled to receive a sign bit of a digital unary input signal, an n bit parallel binary count output connected to the first n bit input of the magnitude comparator, and a clock input; a second n bit counter having a clock input coupled to receive a constant rate clock signal and an n bit parallel binary count output connected to the second n bit input of the magnitude comparator; an AND gate having a first input coupled to receive the constant rate clock signal in frequency divided form and a second input coupled to receive a magnitude portion of the digital unary input signal, and further having an output connected to the clock input of the first counter; and wherein the comparator continually generates an output signal indicative of the relative magnitudes of the counts of the first and second counters, whereby said output signal is a PWM output signal with an average value representing a ramp voltage having a slope determined by magnitude portion of the digital unary input signal with a direction of a slope of the output signal being determined by the polarity of the sign bit.
Owner:YAMAHA CORP

Method and apparatus for sampling digital data at a virtually constant rate, and transferring that data into a non-constant sampling rate device

An improved data acquisition system interface provides virtually constant sampling of input signals and provides those signals in a digitized format to a data acquisition unit that may not be able to sample at a constant rate without missing or “losing” some of the samples. The present invention acts as a front end interface that temporarily latches the sampled data, expands the data into multiple parallel signals, then stores the multiple parallel signals in a dual-port FIFO memory unit. Finally, the multiple parallel signals are transferred into the data acquisition unit at a lower frequency, and the transfer operations take place only when the data acquisition unit is ready to accept data. Since the front end misses no sampling intervals (i.e., it always takes a sample according to an extremely constant frequency crystal clock), then the data acquisition unit will be provided with all of these samples without losing any data. The only requirement is that the data throughput of the multiple parallel signals into the data acquisition unit be greater than or equal to the data sampling rate of the original signal at the front end. The present invention can be used with pure digital signals to capture their precise times of logic state transitions, or with serial data signals in which the precise moments of transition can be used to decipher the serial data. Moreover, the interface can be used with analog signals that are digitized using an analog-to-digital converter.
Owner:LEXMARK INT INC
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