222results about "Television with combined individual color signal" patented technology

An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC / PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC / PAL / SECAM / S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I / O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

A communication method of transmitting video data which may include a predetermined number of bits as a unit from a source device to a sink device in sync with pixel clock and using individual transmission lines for respective color data or the like, may include preparing video data for three-dimensional display including the video data for a left eye and the video data for a right eye; forming the data for the left eye and for the right eye including the predetermined number of bits per pixel respectively; adding one of the data for the left eye and data for the right eye to the other thereof per pixel; forming the data of one pixel including twice the predetermined number of bits and transmitting the data at a timing in sync with the pixel clock; and transmitting the data for three-dimensional display from the source device to the sink device.

A video and graphics system processes video data including both analog video, e.g., NTSC / PAL / SECAM / S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC / PAL / SECAM / S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I / O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

A scalable encoding and decoding method and apparatus based on color information of moving pictures are provided. The color video encoding method comprises: generating an encoded luminance bitstream by encoding a luminance component using a motion prediction based encoding method; and generating at least one encoded chrominance bitstream by encoding at least one color format chrominance component using a motion vector generated by the motion prediction based encoding method. Using this method, storage, transmission, and reproduction of a moving picture can be efficiently performed by scalably encoding the moving picture according to a color format in which the moving picture is encoded.

An electronic endoscopic apparatus having various sorts of electronic endoscopes mounting a CCD with a different number of pixels, for example, 410,000 pixels, 270,000 pixels or 190,000 pixels that are connectable to a processor. A CCD drive and signal processing circuit drives all the CCDs at a frequency set up for the CCD with 410,000 pixels, and an information quantity conversion circuit expands an image acquired by the CCD with 270,000 pixels or 190,000 pixels by pixel interpolation in a horizontal direction or a vertical direction to form an image with an aspect ratio of 4 to 3. Also, a video signal acquired in an NTSC system is converted into a video signal of a PAL system by using a television standard conversion circuit, thereby displaying an excellent PAL video without any bar noise.

A multiplexer of a transmission section generates a clock signal by multiplying a reference clock signal of a digital image signal by a predetermined number ‘K’. A parallel digital image signal is converted into a serial digital signal on the basis of the clock signal, and the serial digital signal is converted into an optical signal in an optical transmission section for transmitting. A demultiplexer extracts a reception clock signal from a serial digital reception signal which is converted into an electric signal in an optical reception section of a reception section, the serial digital reception signal is converted into a parallel signal and a signal corresponding to the parallel digital image signal on the basis of the reception clock signal, and a clock signal corresponding to the reference clock signal is recovered by multiplying the reception clock signal by ‘1 / K’.

A mobile communication apparatus capable of notifying a user of the presence of reproduction waiting information like a short message with proving the user with an impact. A controller of the mobile communication apparatus decides, when a flip is opened, whether the reproduction waiting information is stored in a RAM. If it is stored, the controller displays on a screen a window image including an icon associated with the reproduction waiting information. If there are more than one pieces of the reproduction waiting information, multiple icons are displayed in the window image. One of the icons is selected by placing the cursor on it, so that the reproduction waiting information associated with the icon is replayed in response to the operation of a memory key by the user.

A display control apparatus controls a multi-view display apparatus that displays separate pictures for a plurality of viewing directions on a single screen. The display control apparatus includes a control unit that controls an output of the pictures based on a relationship between the pictures.

A method and apparatus for connecting a plurality of digital video recorders to a plurality of video transmitters via first transmission lines and for connecting the plurality of digital video recorders to a playback receiver via second transmission lines. The playback receiver incorporates an external synchronizing generator for externally synchronizing the plurality of the digital video recorders and the video transmitters. The recorders receiving the video signals generate and inject into the output signals a signal corresponding to identification codes allotted to each video signals. The playback receiver has a selection control circuit receiving selectively and synchronously any individually coded playback or monitored signal, or multiple playback or monitored signals which are displayed individually or in a split screen, respectively. The digital video recorder includes a time-date signal generator and a processing circuit compressing the video signals and outputting them with an injected identification code and time and date of the recorded signals and storing the signal into at least one memory device in an endless rotation, wherein freshly stored signals replace the oldest stored signals.

A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles. The use of the predetermined addressing patterns also results in transferring the compressed video data over the data bus between the memory controller and the video decoder in a less number of clock cycles.

Systems and methods are provided for analyzing material properties of an object using hyperspectral imaging. An exemplary method includes obtaining a hyperspectral image of an object; analyzing the hyperspectral image according to an algorithm; and correlating data obtained from the analysis with material properties of the object.

A method and system for determining surface topology of a three-dimensional (3D) structure, based on a structured pattern that is projected onto the surface structure, and images of the pattern superposed on the structured surface are analysed to provide surface coordinates of the structure. The pattern comprises a plurality of unique color edges defined between pairs of differently-colored stripes, which substantially overcomes ambiguity problems. In one embodiment, a calibration method is provided enabling the surface coordinates to be obtained from a single image of the structure.

An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides multiple time-base clocks for two transport streams. Transport processor circuitry uses multiple PCRs to track transport streams through decoding, storage and or delivery of the decoded signals for display. Provision of a multiple time-base clock for decoding and delivering multiple transport streams allows display of the two decoded audio-video signals on independent monitors.

An image display method including dividing an original image for one frame period into a plurality of subfield images, arranging the subfield images in a direction of a time axis in an order of brightness of the subfield images, and displaying the arranged subfield images in the order of the brightness.

A system for constructing seamlessly viewable multimedia content from selectably presentable multimedia content blocks includes a block definition module for facilitating creation and modification of the content blocks. The block definition module includes a media assignment submodule for associating a synchronized audio and video segment with a content block. Also included is a block linking submodule for creating seamless connections between content blocks, whereby a transition between the connected blocks occurs substantially without interruption upon viewing the multimedia content. The block definition module further includes a layer submodule for associating an interactive layer having interactive controls with the content block.

A method and system for determining surface topology of a three-dimensional (3D) structure, based on a structured pattern that is projected onto the surface structure, and images of the pattern superposed on the structured surface are analysed to provide surface coordinates of the structure. The pattern comprises a plurality of unique color edges defined between pairs of differently-colored stripes, which substantially overcomes ambiguity problems. In one embodiment, a calibration method is provided enabling the surface coordinates to be obtained from a single image of the structure.

In a content reproducing apparatus for displaying three dimensional image using image data for the right eye and left eye, stored after being downsampled in order to reduce data, a high quality image is obtained even at the scene changes or in still pictures. The content reproducing apparatus includes a similar region detector (20) for detecting, for each region forming part of each of the right image and left image, a region of the same size as said each region, and having image data similar to the image data of said each region, and image interpolation data generating circuit (21) for generating interpolation data by extracting data from the similar region, and a frame synthesizing circuit (22) for interpolation the image interpolation data in the decoded image data for each eye.

A receiver for orthogonal frequency division multiplexing (OFDM) signals, including an A / D converter for converting received analog signals to a digital signal data stream and an OFDM demodulator for producing a first set of complex I and Q components of subcarriers from the digital signal data stream. The receiver includes a CSI estimator for estimating Channel State Information (CSI) from the sets of complex I and Q components and a TPS decoder for decoding TPS data from the sets of complex I and Q components using the CSI.

An image display method including dividing an original image for one frame period into a plurality of subfield images, arranging the subfield images in a direction of a time axis in an order of brightness of the subfield images, and displaying the arranged subfield images in the order of the brightness.

A method (300) of converting interlaced Moving Picture Experts Group (MPEG) video signals to progressive video signals can include receiving an interlaced video signal representing a luma component specifying luma lines and a chroma component specifying chroma lines (310) wherein the chroma component can specify approximately one-half the number of lines of the luma component. The interlaced video signal can be decoded and the number of the chroma lines can be increased to approximately the same as the number of the luma lines (320). The number of chroma lines of the interlaced video signal then can be decreased (340), to substantially reverse the previous increase. The interlaced video signal then can be deinterlaced to produce a progressive video signal (350), which can be processed further (360) as needed.

An image zooming apparatus and method for zooming a specific portion of an image in a vertical direction for a digital TV is disclosed. The present apparatus includes a line memory unit for storing the input images; an input data controller for storing the input data in the line memory unit according to a type of the input image and zoom magnification; a zoom controller for receiving zoom area information and zoom magnification from a user, and controlling the data storage in the line memory unit and the processing of the stored data; and data processor for providing a zoomed image according to the control of the zoom controller. The present invention allows a user to zoom an image area of interest and re-zoom a zoomed image area of interest, thereby providing a user-friendly device.

The invention enables the transmission of continuous complex numbers using a symbol based transmission scheme such as OFDM. Accordingly, complex numbers are mapped to the constellation map, enabling a fine granularity of constellation points. This scheme may be used, for example, in the transmission of video where the coefficients representing the higher frequency of each of the video components, as well as the quantization error values of the DC and near DC components, or some, possibly non-linear transformation thereof, are sent as pairs of real and imaginary portions of a complex number that comprises a symbol.

An enterprise KVM system using single twisted pairs to transmit video and data signals is described together with circuitry for the parts of the system and a method of transmitting the signals. The method transmits a video signal and peripheral data over a single twisted pair between a computer and a plurality of peripherals. A sequence of a plurality of analogue video color signals with a vertical synchronisation signal following each analogue video signal is transmitted from the computer to the plurality of peripherals. Peripheral data is transmitted between the plurality of peripherals and computer during the vertical synchronisation signal transmission periods. The KVM enterprise system comprises a plurality of user stations, each user station including a keyboard, mouse and video display connected to a user interface. A plurality of computers are provided each connected to a dongle and supplying video, keyboard and mouse signals to the dongle. A KVM matrix switch is also included. Each of the dongles is connected to the matrix switch by a respective single twisted pair cable. Each of the user interfaces is connected to the matrix switch by a respective single twisted pair cable. Video signals and keyboard or mouse signals are transmitted via the twisted pair cables between any one of the plurality of computers and any one of the user stations.

A receiver for orthogonal frequency division multiplexing (OFDM) signals, including an A / D converter for converting received analog signals to a digital signal data stream and an OFDM demodulator for producing a first set of complex I and Q components of subcarriers from the digital signal data stream. The receiver includes a CSI estimator for estimating Channel State Information (CSI) from the sets of complex I and Q components and a TPS decoder for decoding TPS data from the sets of complex I and Q components using the CSI.

A microscope image pickup system includes: alight source; an object lens; a display device; a record device; a capture device for performing a preview mode in which an image of the test object obtained by the object lens is repeatedly captured and a plurality of captured images are continuously displayed on the display device, or an image record mode in which the image of the test object is captured and the captured image is recorded on the record device; an illumination light amount control device for controlling the amount of light of the illumination light; and a system control device for controlling an operation of the illumination light amount control device depending on the preview mode or the image record mode performed by the capture device.

An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.