Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Traversal test method of configurable logic block (CLB) of field programmable gate array (FPGA) based on look-up table structure

A technology of traversal testing and programming logic, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., to achieve the effects of reducing occupation, reducing configuration times, and good portability

Active Publication Date: 2010-10-20
FUDAN UNIV
View PDF6 Cites 27 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But it is basically limited to the basic function of the flip-flop - the test of the latch data

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Traversal test method of configurable logic block (CLB) of field programmable gate array (FPGA) based on look-up table structure
  • Traversal test method of configurable logic block (CLB) of field programmable gate array (FPGA) based on look-up table structure
  • Traversal test method of configurable logic block (CLB) of field programmable gate array (FPGA) based on look-up table structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] LUT single point fault traversal test scheme such as image 3 shown. Here, two CLBs are regarded as a repeatable cell, and A1, A2, A3, and A4 come from the IO port or the output of the previous cell. Each LUT is configured as XOR, so that B1, B2, B3, and B4 are all equal to A1@A2@A3@A4; C1=B1@A2@A3@A4=A1, C2=A2, C3=A3, C4= A4. It can be seen that the output of each cell is equal to the input. In this way, as long as the 8 LUTs in a cell are fully tested, the entire row of CLBs can be fully tested. We can achieve the purpose of traversing each memory cell of each LUT in the first CLB by adding a pseudo-depletion test stimulus (0000 to 1111) to the 4 input terminals of the first CLB. For the second CLB, though, the input is no longer {A1, A2, A3, A4}, but three of these four and A1@A2@A3@A4. But obviously it is also traversed from 0000 to 1111, but the order has changed. In the second configuration, replace the XOR with the same OR. At the same time, due to the two...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention belongs to the technical field of an integrated circuit, in particular to a traversal test method of a configurable logic block (CLB) of a field programmable gate array (FPGA) based on a look-up table (LUT) structure. The method comprises: carrying out traversal tests on the single-point fault of an LUT, testing the multiple-point fault of the LUT, carrying out traversal tests on a distributive RAM, assigning the initial value of the trigger to be 0 or 1, carrying out level fixing on a setting terminal and a resetting terminal, leading the enabling to be invalid, and carrying out traversal tests on setting, resetting and enabling and the like. The invention can complete all the tests on the confronting manufacturing of all the CLBs in FPGA chips, and can cover all the basic logic devices, programmable code points and internal interconnection resources inside the CLBs. The configuration times, configuration difficulty and test time required by the test can all be greatly optimized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a traversal test method for a programmable logic unit in an FPGA (Field Programmable Gate Array). Background technique [0002] The hardware programmable feature of FPGA enables it to greatly reduce the development risk and development cost of electronic systems, shorten the time to market, and reduce maintenance and upgrade costs through in-system programming, remote online reconfiguration and other technologies, so in communication, control, numerical calculation, etc. field has been widely used. [0003] The continuous expansion of FPGA scale and application field also makes the traversal test of FPGA gradually become urgent and difficult. First of all, FPGA itself is a general-purpose device, and it needs to be programmed and configured to realize specific functions. Therefore, FPGA testing must also be general and has nothing to do with applications;...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G01R31/3185
Inventor 付勇陈利光王健王元来金梅
Owner FUDAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com