Method for correcting offset of high-speed high-precision large-range low-power-consumption dynamic comparator

A technology of dynamic comparator and correction method, applied in the direction of analog/digital conversion calibration/test, etc., can solve the problems of limited accuracy, limited minimum capacitance value, nonlinearity, etc., and achieve the effect of low power consumption
CN102843136AActive Publication Date: 2012-12-26FUDAN UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
FUDAN UNIV
Publication Date
2012-12-26

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Abstract

The invention belongs to the technical field of integrate circuits and in particular relates to a method for correcting offset of a high-speed high-precision large-range low-power-consumption dynamic comparator. The comparator is a core part of an analog-to-digital converter. The invention provides a new real-time correction method. By utilization of the characteristic that the capacitance value of variable capacitance of a metal oxide semiconductor (MOS) tube working in an inversion layer is linearly continuously variable along with the regulating voltage, load capacitance at the output end of the comparator is subjected to fine adjustment precisely until the differential input of the comparator is zero. The offset voltage generated by mismatch of devices of the comparator and the influence generated by fine adjustment on the output load capacitance of the comparator are counteracted mutually, so that the offset voltage of the comparator is corrected. By the method, the 1sigma offset voltage of the comparator can be effectively reduced by three hundred times and can be reduced to 66 MuV from the typical value of 29.4 mV.
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Description

technical field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a comparator offset correction method caused by device size mismatch or PVT fluctuation. Background technique

[0002] High-speed dynamic comparators are increasingly used due to their low power consumption, such as successive approximation analog-to-digital converters (SAR ADC) and flash analog-to-digital converters (Flash ADC). Although the power consumption of the dynamic comparator is further reduced and the speed is further improved with the progress of the technology, the device mismatch caused by the shrinking of the size becomes more and more serious, which greatly limits the resolution of the dynamic comparator. In order to reduce this offset voltage, the traditional approach is to add a pre-amplification (Op-Amp) to the front end of the dynamic comparator. But the pre-amplification circuit consumes a lot of power and limits the speed that the dy...

Claims

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