Method for correcting offset of high-speed high-precision large-range low-power-consumption dynamic comparator

Abstract

The invention belongs to the technical field of integrate circuits and in particular relates to a method for correcting offset of a high-speed high-precision large-range low-power-consumption dynamic comparator. The comparator is a core part of an analog-to-digital converter. The invention provides a new real-time correction method. By utilization of the characteristic that the capacitance value of variable capacitance of a metal oxide semiconductor (MOS) tube working in an inversion layer is linearly continuously variable along with the regulating voltage, load capacitance at the output end of the comparator is subjected to fine adjustment precisely until the differential input of the comparator is zero. The offset voltage generated by mismatch of devices of the comparator and the influence generated by fine adjustment on the output load capacitance of the comparator are counteracted mutually, so that the offset voltage of the comparator is corrected. By the method, the 1sigma offset voltage of the comparator can be effectively reduced by three hundred times and can be reduced to 66 MuV from the typical value of 29.4 mV.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a comparator offset correction method caused by device size mismatch or PVT fluctuation. Background technique [0002] High-speed dynamic comparators are increasingly used due to their low power consumption, such as successive approximation analog-to-digital converters (SAR ADC) and flash analog-to-digital converters (Flash ADC). Although the power consumption of the dynamic comparator is further reduced and the speed is further improved with the progress of the technology, the device mismatch caused by the shrinking of the size becomes more and more serious, which greatly limits the resolution of the dynamic comparator. In order to reduce this offset voltage, the traditional approach is to add a pre-amplification (Op-Amp) to the front end of the dynamic comparator. But the pre-amplification circuit consumes a lot of power and limits the speed that the dy...

AI Technical Summary

Problems solved by technology

However, the existing correction algorithms all have various defects.

[0003] One of the two currently popular correction methods is to adjust the output load of the dynamic comparator through an auxiliary digital-to-analog converter (AUX-DAC), but this method is limited by the minimum capacitance value that can be obtained, and it is discontinuous, so The accuracy that can be obtained is not high; when there is a large offset in the comparator to be corrected, a large AUX-DAC is required (to achieve N-bit linearity, 2 N capacitor or resistor), will severely limit the operating speed of the comparator

Another method is to add an additional input tube at the input end as a current source. Although this correction method can achieve continuous adjustment, the current and input voltage of the input tube used as a current source have a square relationship, and there is serious nonlinearity. Therefore, It also greatly limits the accuracy that can be achieved

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