231results about "Frequency-changer modifications" patented technology

A frequency conversion circuit of the present invention includes: (i) a first mixer for mixing the radio frequency signal having a frequency fRF with a first oscillation signal having a frequency fLO1 so that the radio frequency signal is downconverted into an intermediate frequency signal; and (ii) a second mixer for mixing the intermediate frequency signal sent from the first mixer with two local oscillation signals so that the intermediate frequency signal is downconverted into two base-band signals having different phases. The second local oscillation signals have phases of 0° and 270°, respectively. These frequencies satisfies: <?in-line-formulae description="In-line Formulae" end="lead"?>fLO1=kxfRF(k>1) <?in-line-formulae description="In-line Formulae" end="tail"?> <?in-line-formulae description="In-line Formulae" end="lead"?>fLO2=fLO1 / m, (m>1)<?in-line-formulae description="In-line Formulae" end="tail"?> <?in-line-formulae description="In-line Formulae" end="lead"?>k=m / (m-1).<?in-line-formulae description="In-line Formulae" end="tail"?> This arrangement ensures (i) a small frequency conversion circuit that can be mounted on an integrated circuit, (ii) a radio frequency receiver including the frequency conversion circuit, and (iii) a radio frequency transceiver including the radio frequency receiver.

An image rejection mixer of reduced power dissipation includes a signal distributor supplied with local signals having a phase difference to distribute the local signals, a first and a second signal mixer for mixing the distributed local signals and RF signals having a phase difference and outputting respective IF current signals, a phase shifter for shifting in phase the respective mixed IF current signals so as to provide them with a relative phase difference of 90 degrees, and a signal adder for adding the respective phase shifted intermediate frequency current signals. The shifter shifts the phases of the respective IF current signals outputted from the first and the second signal mixers.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.