682results about "Electrial characteristics varying frequency control" patented technology

A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

The present invention provides for a system and method for improvement of radio transmitter and receiver frequency accuracy for a local radio communication unit that communicates digital data with a remote communication unit. In the local unit the received radio signal is down-converted, and converted to complex baseband digital samples by an analog-to-digital converter. A downlink digital phase rotator applies a fine frequency shift to the samples in accordance with a receiver frequency offset command. The resultant baseband signal is used by the data demodulator and by a receiver frequency error estimator to obtain receiver frequency errors. A data modulator generates baseband complex samples which are shifted in carrier frequency by an integrated uplink digital phase rotator in accordance with a transmitter frequency offset command. The modulated samples are then converted by a digital-to-analog converter and upconverted in frequency for radio transmission to the remote unit. The local oscillator signals for both upconverter and downconverter are phase locked to a reference frequency generated by a VCXO. An automatic frequency control (AFC) function nulls the transmitter and receiver frequency error by the frequency adjustment commands to the uplink and downlink phase rotators or to the VCXO digital-to-analog converter (VCXO DAC) by feedback control principals based on measured receiver frequency error. During frequency track mode when communications between local and remote units are possible, the AFC only adjusts radio frequency via phase rotator commands and the VCXO command remains fixed, thereby avoiding communications performance degradation by VCXO frequency quantization error due to the VCXO DAC. The AFC adjusts VCXO frequency only during a preliminary acquisition mode prior to data communications, or to back out excessively large frequency offsets accumulated in the downlink and uplink phase rotators during track mode. When a VCXO adjustment is made in track mode, phase rotator adjustments are simultaneously applied to cancel the errors in transmitter and receiver radio frequencies caused by the step change due to VCXO frequency quantization thereby mitigating VCXO frequency quantization noise.

A self-calibrating radio frequency transmitter includes an adjustable oscillator, a first frequency counter, a second frequency counter, and a comparer. The radio frequency transmitter is powered by an AC power line, which presents a line frequency. The transmitter contains an adjustable frequency oscillator that oscillates at an oscillator frequency and has a desired operating frequency. The first frequency counter counts the oscillator frequency while the second frequency counter counts the line frequency. The comparer compares the counted oscillator frequency to the counted line frequency and produces an output representative of the difference between the counted line frequency and the counted oscillator frequency. This difference in frequency indicates a deviation in the oscillator frequency from the desired operating frequency. The output from the comparer is input to the oscillator to adjust the oscillator frequency back to the desired operating frequency.

A device calibrates the frequency of an oscillator. The oscillator has first and second inputs and generates an output frequency responsive to a first voltage signal at the first input. The calibration device generates a calibration signal applied at the second input of the oscillator for calibrating its output frequency and comprises a counter. The counter has a first input frequency proportional to a reference frequency and a second input frequency proportional to the output frequency. The counter counts the time window number given by the ratio of the second to first frequencies. The device comprises a comparator that compares the counted time window number with a prefixed time window number. The calibration device changes the value of the calibration signal if the counted time window number is different from the prefixed time window number and until the counted time window number is equal to the prefixed time window number.

A correction processor connected to an oscillator uses precision timing signals propagated over a digital network to generate an error signal. IEEE-1588 time synchronization protocols produce precision time signals which are converted to precision interval signals. The correction processor uses the precision interval signals to count pulses of the oscillator. A correction circuit compares the counter output with a predetermined value and generates an error signal may be used to correct the oscillator or may be propagated to consumers of the oscillator. An arbitrary reference oscillator may be used to generate the precision timing signals propagated on the network, to slave other oscillators to it. The precision of the reference oscillator may be deliberately overstated to insure it is used as a master.

Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures.

Various systems, methods and apparatus for calibrating a clock generating circuit are discussed herein. As one example, a method for calibrating a voltage controlled oscillator is disclosed. The method includes fixing the control voltage of a fine tune capacitor in the voltage controlled oscillator at a predetermined level. A binary search is performed in a digital circuit for a value of a calibration word that is used to enable switched capacitors in a coarse tune capacitor bank in the voltage controlled oscillator. The calibration word is fixed at the value determined by the binary search, and the control voltage of the fine tune capacitor is released to enable adjustment of the control voltage by a feedback signal to the voltage controlled oscillator.

Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.