109 results about "Process corners" patented technology

The invention discloses an early-stage process corner time sequence prediction method based on deep learning, an electronic device and a storage medium, and aims to capture an interaction relationship between units in a path, an early-stage time sequence prediction process is established based on a bidirectional long-short-term memory network. The time sequence and the physical information of each level of unit in the path are represented as a sequence, and the information in the sequence is transmitted and represented through the BLSTM to learn the mutual influence between the units in the path, so that the path delay after layout is accurately predicted. On the basis, the influence of the global feature of the path on the path time sequence after layout is learned by using the multi-layer perceptron network, so that the prediction precision is improved, and meanwhile, an early time sequence prediction framework is adapted to a scene of various process corners. Based on the prediction result, the iteration of the design is reduced, and the time cost of the chip design is reduced.

The invention relates to the technical field of chip verification, in particular to a front-end low-power-consumption verification environment generation method, electronic equipment and a medium, and the method comprises the steps: S1, obtaining register transfer level code information An and unified power consumption format information Bn of a chip; s2, acquiring a target configuration file; s3, analyzing the target configuration file, if Cn is set as a first identifier, adding A1n and B1n into a target compiling file list, and if Cn is set as a second identifier, adding A2n and B2n into the target compiling file list; s4, screening the standard cell library information file corresponding to at least one process corner from each standard cell library information file, and adding the standard cell library information file into a target compiling file list; and S5, compiling and generating a front-end low-power-consumption verification environment based on the target compiling file list. According to the invention, the generation efficiency and accuracy of the front-end low-power-consumption verification environment are improved.

The invention belongs to the technical field of integrated circuit post-simulation verification, and discloses an integrated circuit post-simulation system and method based on BFM and SDF inverse labeling, the system comprises a BFM packaging module used for describing a time sequence path of a port output signal and instantiating a BFM module or connecting an interface signal of a verification IP, an SDF generating assembly used for generating a BFM signal, and an SDF generating assembly used for generating an SDF signal. The static time sequence analysis database module is used for extracting delay information corresponding to a port output signal in a BFM or verification IP interface from the static time sequence analysis database and generating an SDF file according to the delay information, and the top layer verification environment module is used for reversely marking the SDF file to the BFM packaging module and running a test case. According to the method, the delay information of the BFM under each process corner is rapidly extracted by using the SDF generation component, the independent SDF file is generated and is reversely marked to the BFM packaging module, so that a real port time sequence can be simulated, multiple iterations are not needed, a large amount of manpower and time cost is saved, the delay information adding speed of the BFM is remarkably improved, and the error rate is reduced.

Embodiments of the present disclosure provide a storage chip and a storage system. The storage chip is configured such that characterization parameters representing the process corner of the storage chip are stored therein, and a reference voltage with an adjustable magnitude is further provided therein. The magnitude of the reference voltage is adjustable based on the characterization parameters, and the storage chip adjusts the delay of data read from a storage unit to output from a data port based on the reference voltage. Embodiments of the present disclosure are beneficial to improving the neatness of data signal transmission and preventing data conflicts.

The invention provides a method and a system for testing and analyzing reliability of an integrated circuit under an extreme working condition, and relates to the technical field of testing. Identifying a limit working condition point under the critical state of the circuit function constraint condition; injecting random deviation to simulate circuit behaviors under different process corners to obtain reliability characteristic parameters; establishing a correlation model of a device degradation state and circuit function margin attenuation to predict life distribution; and determining a reliability level according to the life distribution and a preset threshold and generating a test report. The failure mode under the limit working condition can be accurately positioned, and the integrated circuit life prediction accuracy is improved.

An SRAM architecture is disclosed that provides a process- and temperature-compensated word-line underdrive scheme enabling stable, low-voltage operation. Each row decoder generates an initial word-line signal, derives an inverse word-line signal, and drives the corresponding word line through driver circuitry including a word-line underdrive p-channel transistor. The transistor's gate is controlled by the inverse word-line signal and optionally receives a dynamically generated negative bias to reduce device size while maintaining performance. Control circuitry includes a word-line underdrive sink circuit having dummy memory cells that replicate bit-cell behavior to generate a compensated driver output signal tracking process and temperature variations. A negative bump generator produces a transient below-ground potential at the gate node to enhance underdrive efficiency. This improves bit-cell stability, dynamic noise-margin yield, and performance uniformity across process corners and temperature, while minimizing silicon area.

This application provides a security monitoring method and a microprocessor architecture. The method is applied to a microprocessor architecture including a processor core and a security monitoring module. The security monitoring module includes a ring oscillator with adjustable inverter stages. The method includes: when the security monitoring module detects a change in the process corner of the ring oscillator, it adjusts the inverter stages of the ring oscillator according to the current process corner of the ring oscillator and the operating frequency of the monitored module, so that the operating frequency of the ring oscillator is consistent with the operating frequency of the monitored module. The monitored module includes any module in the microprocessor architecture, and the ring oscillator serves as a reference frequency source for security monitoring of the monitored module. The above method can provide a stable reference frequency within the microprocessor architecture, thereby improving the accuracy and effectiveness of security monitoring of the monitored module.

The present invention provides a low process angle deviation delay circuit, including a low process angle deviation current mirror circuit and a delay module. The low process angle deviation current mirror circuit generates two currents according to its own input voltage, and adjusts its own device parameters so that the two currents are opposite to the process angle variation coefficient, inputs the two currents into the delay module, and controls the delay module to start. The delay module generates a fixed time delay signal through its own charging and discharging process. The present invention greatly reduces the large delay changes caused by the process angle change by the mutual cancellation of the two currents relative to the process angle variation coefficient, so that the delay module can generate a delay signal with a set time and is not affected by the process angle deviation. The delay signal of the present invention has high accuracy and can be widely used in structures that require a delay circuit.

The invention provides an access control method and equipment of a storage circuit and a storage medium. The memory circuit is provided with a reading unit, also can be called a reading circuit, the reading unit is provided with an electric fuse, and the method comprises the following steps: setting a plurality of different reference resistance values for the reading unit; comparing the resistance value of the electric fuse with any reference resistance value; if the resistance value of the electric fuse is smaller than any reference resistance value, determining that the electric fuse is not burnt; and if the resistance value of the electric fuse is greater than any reference resistance value, determining that the electric fuse is burnt. On the basis, a plurality of reference resistance values used for reading the circuit are set, it is guaranteed that the reference resistance values cover the change range of the process corner, and therefore the product yield can be improved.

A process corner simulation system includes a frequency generator, a transistor sensitive circuit, and a process corner simulator. The frequency generator is used to generate a frequency signal. The transistor sensitive circuit is coupled to the frequency generator for receiving the frequency signal. The process corner simulator is coupled to the transistor sensitive circuit for receiving at least one output signal generated from the transistor sensitive circuit. The at least one output signal outputted from the transistor sensitive circuit includes speed information and duty cycle information. The process corner simulator uses a plurality of process corner models for generating a plurality of simulation results corresponding to different process corners according to the at least one output signal.

The present invention provides a method for determining a simulation model, a method for classifying chips, and related devices. The method for determining the simulation model includes: obtaining test data of semiconductor devices fabricated under various process corner conditions, where the semiconductor devices include wafers on which multiple chips are fabricated, and the test data includes the test data of the chips; dividing the semiconductor devices into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model, and the similarity between the test data of the chips in different regions and the simulation data is different; determining adjustment values of the simulation parameters of the initial simulation model according to the test data of the chips in different regions, and obtaining optimal simulation models corresponding to the chips in different regions respectively, so as to perform simulations on the chips in different regions based on the optimal simulation models and improve the accuracy of the simulation by the simulation model.

The invention relates to the technical field of initiating explosive device detonating, and discloses a detonating control chip adjusting method and system. The adjustment and calibration method is applied to the control chip adjustment and calibration equipment and specifically comprises the following steps that S101, a control chip adjustment and calibration request sent by a terminal is received, and the control chip adjustment and calibration request comprises a Tr imCode code pre-implanted in a control chip and target parameters of control chip adjustment and calibration; s102, acquiring a Tr imCode code, performing circuit simulation on an oscillator on the designed control chip, acquiring a temperature drift simulation result of the oscillator, and determining whether the temperature drift simulation result of the oscillator can counteract a deviation introduced by a process corner parameter or not; s103, if it is determined that the temperature drift simulation result of the oscillator can counteract the deviation introduced by the process corner parameters. An isolation protection circuit of a high-voltage circuit, a digital circuit and an analog circuit is designed for the control chip, circuit isolation and power isolation are adopted, and efficient high-voltage high-power control and high-precision timing control functions are achieved respectively.

The invention belongs to the technical field of integrated circuits, and particularly relates to a positive temperature coefficient current generating circuit with process compensation. The circuit comprises a symmetric positive temperature coefficient current generating circuit or a complementary positive temperature coefficient current generating circuit. The symmetrical positive temperature coefficient current generation circuit comprises two positive temperature coefficient sub-current generation circuits; wherein one sub-current generating circuit comprises a positive temperature coefficient current biasing circuit with NMOS (N-channel metal oxide semiconductor) process characteristics, a first operational amplifier circuit and a first current mirror circuit; the other sub-current generating circuit comprises a positive temperature coefficient current biasing circuit with PMOS (P-channel Metal Oxide Semiconductor) process characteristics, a second operational amplifier circuit and a second current mirror circuit; the complementary positive temperature coefficient current generating circuit comprises a positive temperature coefficient current biasing circuit with dual-process characteristics, a third operational amplifier circuit and a third current mirror circuit; according to the invention, the asymmetry of a temperature curve caused by the asymmetry of a process corner can be effectively compensated while the positive temperature coefficient current is generated, so that the device has a good application prospect.

The present invention discloses a filter with process angle temperature compensation, comprising a fully differential operational amplifier, first to sixth resistor matrices, and first to third capacitors, wherein the first end of the first resistor matrix is connected to the positive differential input terminal, the second end of the first resistor matrix is connected to the first end of the third resistor matrix, the first end of the third capacitor, and the first end of the fifth resistor matrix, the first end of the second resistor matrix is connected to the negative differential input terminal, the second end of the second resistor matrix is connected to the first end of the fourth resistor matrix, the second end of the third capacitor, and the first end of the sixth resistor matrix, the second end of the third resistor matrix is connected to the positive input terminal of the amplifier and the first end of the first capacitor, the second end of the fourth resistor matrix is connected to the negative input terminal of the amplifier and the first end of the second capacitor, the second end of the fifth resistor matrix is connected to the second end of the first capacitor and the negative output terminal of the amplifier, and the second end of the sixth resistor matrix is connected to the second end of the second capacitor and the positive output terminal of the amplifier. The present invention can achieve good filtering characteristics.

The invention provides an error checking and correcting circuit and a memory, and the circuit comprises a first time sequence regulation and control circuit, a second time sequence regulation and control circuit, a reading amplification circuit, an operational circuit, a time sequence matching circuit and a latch circuit, the time delay and the wiring time delay of the first time sequence regulation and control circuit, the reading amplification circuit and the operation circuit are matched through the second time sequence regulation and control circuit and the time sequence matching circuit, so that the time delays of control signals and operation time in the circuits are basically close under different process angle, voltage and temperature conditions, and the waiting time can be shortened; the read-out error correction efficiency of the circuit is improved while asynchronous data signal acquisition is completed, the circuit structure is simple, the used circuit area is small, and the time sequence matching circuit does not involve winding on the circuit layout, so that the time delay effect close to the circuit can be obtained on the premise that wiring matching is not performed, and the circuit reliability is improved. And meanwhile, a part of area is saved, and the flexibility is improved.

This application relates to a method, apparatus, processing equipment, and readable storage medium for processing corner connection speeds. The method includes: acquiring the corner constraint speeds of adjacent sub-processing trajectories; determining the local extrema of the corner constraint speeds based on the corner constraint speeds; and determining the planned corner connection speed of the sub-processing trajectories based on the corner constraint speeds, the local extrema of the corner constraint speeds, and speed planning model data of the sub-processing trajectories. The local extrema of the corner constraint speed is the speed of one endpoint of the sub-processing trajectory, and the planned corner connection speed is the speed of the other endpoint of the sub-processing trajectory. This method ensures that the speed of the other endpoint of the sub-processing trajectory is not too large or too small, and that the speeds of both endpoints of the sub-processing trajectory meet the requirements of the aforementioned speed planning model data. This prevents processing equipment (such as cutting equipment) from experiencing processing problems or incomplete processing (such as overcutting or undercutting) during actual processing, thereby improving processing quality.

Technologies and implementations for a voltage management circuit. The voltage management circuit may be configured to facilitate management of behavior of electronic devices including management of process corners associated with semiconductor integrated circuit devices. The technologies and implementations may facilitate a controlled amplitude for a signal that may be configured to push a negative ground capacitor. The amplitude may decrease as a process corner becomes faster.

The present invention discloses a physical construction method suitable for meeting triple modular redundancy. In the layout stage, a customized design is adopted for the clock management unit. The three registers in the same group are effectively controlled through scripts during implementation. Since the existing triple modular registers increase the clock delay and have the characteristic of large delay differences under different process corners in advanced processes, the difficulty of timing convergence is reduced, and the design efficiency is effectively accelerated. Finally, the triple modular clock phase difference check is completed by using the clock length comparison method. The present invention can ensure that the single event effect is effectively improved while ensuring that the triple modular design quickly meets the design specifications. The present invention has the advantages of simple process, strong operability, and fast timing convergence speed, and can meet other tape-out sign-off conditions.

The invention discloses a low-power-consumption reference source, which belongs to the technical field of integrated circuit design and comprises a current biasing circuit and a reference voltage generating circuit. The current bias circuit isolates fluctuation change of the power supply voltage while reducing the power supply voltage through a depletion type transistor, and outputs bias current; according to the reference voltage generation circuit, a parallel enhanced transistor which works in a sub-threshold region and adopts a hybrid bias mode is used as a load, and a reference voltage which is subjected to temperature compensation, low in power consumption and not changed along with temperature fluctuation is obtained according to a bias current. Besides, the method can be realized only through ingenious planning of body end connection on a layout level, additional process steps and manufacturing cost are not increased, a flexible and effective compensation dimension is provided for a designer, accurate optimization can be carried out aiming at a specific process corner and a working temperature range, and the method is suitable for large-scale production. And the practicability and the reliability of the reference voltage source in various high-performance analog and digital-analog hybrid integrated circuits are greatly improved.

The invention provides a circuit evaluation method, an optimization method, a device, a system, a terminal and a computer storage medium, and the circuit evaluation method comprises the steps: obtaining each fluctuation parameter range and each simulation parameter value of a circuit under a current production technology; based on each fluctuation parameter range, in combination with a preset process corner parameter framework, obtaining each process corner; for each process corner, simulation is carried out in combination with each simulation parameter value, and simulation data of each process corner is obtained; if the simulation data corresponding to each process corner meets the working requirements of the circuit, the evaluation result of the circuit is passed; otherwise, the evaluation result of the circuit is not passed; wherein the circuit working requirement is used for representing the simulation condition of each process corner of the qualified circuit. Simulation data conforming to the actual measurement performance of the circuit can be obtained by performing analogue simulation on the basis of each constructed process corner, so that the accuracy of an evaluation result is improved.

The invention relates to a reference unit for an eFuse read module and a reference resistance setting method thereof, and aims at an eFuse adopting an AA fuse, the AA fuse uses a diffusion layer and a metal silicide layer thereof as a fuse medium, the AA fuse is different from fuses made of other materials, the AA fuse is mainly electromigration in the eFuse programming process, and the reference resistance of the AA fuse is set. The resistance values before and after fusing have normal distribution characteristics, the intermediate value of the resistance values before and after fusing of the AA fuse wire is used as the reference resistance value, and due to the fact that the state of the reference resistance value is the same as that of an actual fuse wire after fusing, the reference resistance value can be changed to the same degree under different process characteristics and temperatures, and therefore compared with a conventional fixed reference resistor, the resistance value of the AA fuse wire is greatly improved. According to the reference unit provided by the invention, the output deviation of a comparison circuit caused by the fact that a traditional fixed reference resistor cannot track changes is avoided, and the reading reliability of eFuse under various process corner and temperature conditions is greatly improved.

The present application relates to chip verification technical field, especially to a kind of front-end low-power verification environment generation method, electronic equipment and medium, method includes steps S1, the register transfer level code information A of chip is obtained n And unified power consumption format information B n ;Step S2, target configuration file is obtained;Step S3, the target configuration file is parsed, if C n It is set to first identification, then A1 n And B1 n Join target compilation file list, if C n It is set to second identification, then A2 n And B2 n Join target compilation file list;Step S4, at least one process angle corresponding standard cell library information file is screened from each standard cell library information file and joined target compilation file list;Step S5, based on the target compilation file list compiles and generates front-end low-power verification environment.The present application improves the generation efficiency and accuracy of front-end low-power verification environment.

The invention provides an innovative gate-level inverter optimal-inferior trend analysis method and system and a terminal, and the method comprises the steps: collecting the electrical characteristic data and electrical measurement data of a device test key of an inverter, and constructing a physical model for a typical process corner and a variation model for other process corners based on the data; a mature SPICE model verified by a factory is used for gate-level circuit simulation, a trend angle is calculated, and an optimal trend angle is analyzed and determined, so that the device optimization direction is defined. And further correcting the device design according to the optimization direction, and optimizing the manufacturing process parameters of the inverter. According to the method, when the performance of the gate-level inverter is analyzed, the comprehensive influence of local and global deviations is fully considered, the performance change under different process corners is comprehensively evaluated, the accuracy of an optimization result is ensured, and the performance and reliability of a device are effectively improved. Meanwhile, through benchmarking a gate level trend angle and a device process angle, a device optimization direction is defined, clear guidance is provided for a factory device manufacturing direction, device TT value adjustment is assisted, and device performance optimization is promoted.

The invention provides a low-power-consumption low-voltage detector, which relates to the technical field of detectors and comprises a detection branch, a bias branch and an output shaping module, the first end of the detection branch is connected with power supply voltage, the second end is connected with the bias branch, and the detection branch is used for outputting an overturning signal when the power supply voltage reaches set detection voltage; the bias branch is used for providing stable bias voltage for the detection branch and has a temperature compensation function; and the output shaping module is connected with the output end of the detection branch and is used for shaping the overturning signal and then outputting a detection signal. In the mode, ultralow detection voltage, ultralow power consumption, temperature stability, high process angle robustness and small chip area are realized, and the detection voltage is programmable.

The invention belongs to the field of radio frequency circuits, and particularly relates to a process angle self-adjusting circuit and method for controlling overshoot voltage existence duration, and the circuit comprises a judgment voltage generation circuit which is used for generating judgment voltage and outputting the judgment voltage to the positive input end of an upper limit comparator and the positive input end of a lower limit comparator; the window voltage generation circuit is used for generating a window voltage comprising an upper limit window voltage and a lower limit window voltage, outputting the upper limit window voltage to the negative input end of the upper limit comparator, and outputting the lower limit window voltage to the negative input end of the lower limit comparator; the upper limit comparator is used for comparing the judgment voltage with the upper limit window voltage and outputting a high level or a low level; and the lower limit comparator is used for comparing the judgment voltage with the lower limit window voltage and outputting a high level or a low level. By controlling the access number of the time control devices of the overshoot voltage generation module, the process corner control of the overshoot voltage on the existence time performance is successfully realized.

The invention provides a parameter processing method and device.The method comprises the steps that a circuit topological structure and a target manufacturing process under an original manufacturing process are obtained, and the circuit topological structure comprises circuit devices and the connection relation between the circuit devices; the target manufacturing process comprises N process corners of the circuit topological structure, M standard indexes and P candidate parameters of the circuit device; determining N1 representative process corners according to the N process corners; according to the circuit topological structure, the N1 representative process corners, the M1 standard indexes and the P1 candidate parameters, determining a target device parameter, 0 lt, meeting the target manufacturing process, of the circuit topological structure; m1 < = M, 0lt; p1 < = P. According to the method provided by the invention, the design parameter tuning work of the analog circuit device during process migration can be automatically completed, and the chip design quality and efficiency are improved.

This invention relates to the field of chip technology and discloses a chip screening method, apparatus, device, medium, and program product. The method includes: during the chip testing phase, acquiring process corner data corresponding to each initial chip; acquiring the target ambient temperature range and the target thermal design current upper limit; and, through a pre-established target correlation model between ambient temperature, process corner, and the target thermal design current upper limit, acquiring the process corner limitation range based on the target ambient temperature range and the target thermal design current upper limit; and, based on the process corner limitation range and the process corner data, screening out target chips from each initial chip. This method enables chip screening based on the thermal design current upper limit, reduces performance fluctuations between chips, and ensures the operating efficiency of the chip cluster.

The invention discloses a global process corner model, and in a global process corner model architecture, a global process corner of an electrical parameter of a semiconductor device is obtained by adding a TTG process corner of the electrical parameter to a standard deviation of the electrical parameter corrected by adopting an LOD correction function. The LOD correction function comprises an SA correction term, an SB correction term and a first constant term. The SA correction term is a correction term formed by multiplying a power function term of SA by a first channel parameter term. The SB correction term is a correction term formed by multiplying a power function term of the SB by a second channel parameter term. The first channel parameter item and the second channel parameter item have the same structure and at least comprise a second constant item, a power function item of L, a power function item of W and a ghost paper item of WL. Each has fitting parameters determined by fitting. The invention further discloses an extraction method of the global process corner model. According to the method, the fitting precision of the process corner model can be improved, the influence of the process change on the device performance can be reflected more accurately, and finally a more reasonable layout can be designed.

The embodiment of the invention relates to a simulation model, a generation method thereof, a simulation method, electronic equipment and a storage medium. The method comprises the steps that the position of a pseudo global process corner is determined based on the position of a preset global process corner and the correlation between target parameters of the global process corner, and the pseudo global process corner is used for assisting in defining the electrical property distribution range of a simulation object; process corner model parameters corresponding to the target parameters are adjusted based on the values of the target parameters at the positions of the global process corner and the pseudo-global process corner, so that the simulation values of the target parameters are consistent with the target values of the corresponding target parameters; and determining model parameters of the simulation model based on the adjusted process corner model parameters to generate the simulation model. According to the technical scheme, the accuracy of MC simulation can be improved.

A method for implementing timing closure of an ultra-large-scale SOC based on module division includes the following steps: S1, acquiring timing data of a full chipset, and dividing an SOC into three modules; S2, reading lib, lef, netlist and def in each module, determining each specific module requiring timing recovery and each prototype module not requiring timing recovery, reading lib and lef in each specific module, and reading netlist and def in each prototype module; S3, creating multiple process corners and acquiring timing data of each process corner, and back-annotating and reading netlist and def out of the multiple process corners corresponding to each specific module to determine an attribute-maintained part and a to-be-recovered part; and setting the attribute-maintained part and each prototype module to be in a not-to-be-recovered state; and S4, sending out a timing recovery command, and performing timing violation fixing on the to-be-recovered part.