82 results about "Process corners" patented technology

The invention relates to the technical field of chip verification, in particular to a front-end low-power-consumption verification environment generation method, electronic equipment and a medium, and the method comprises the steps: S1, obtaining register transfer level code information An and unified power consumption format information Bn of a chip; s2, acquiring a target configuration file; s3, analyzing the target configuration file, if Cn is set as a first identifier, adding A1n and B1n into a target compiling file list, and if Cn is set as a second identifier, adding A2n and B2n into the target compiling file list; s4, screening the standard cell library information file corresponding to at least one process corner from each standard cell library information file, and adding the standard cell library information file into a target compiling file list; and S5, compiling and generating a front-end low-power-consumption verification environment based on the target compiling file list. According to the invention, the generation efficiency and accuracy of the front-end low-power-consumption verification environment are improved.

The invention belongs to the technical field of integrated circuit post-simulation verification, and discloses an integrated circuit post-simulation system and method based on BFM and SDF inverse labeling, the system comprises a BFM packaging module used for describing a time sequence path of a port output signal and instantiating a BFM module or connecting an interface signal of a verification IP, an SDF generating assembly used for generating a BFM signal, and an SDF generating assembly used for generating an SDF signal. The static time sequence analysis database module is used for extracting delay information corresponding to a port output signal in a BFM or verification IP interface from the static time sequence analysis database and generating an SDF file according to the delay information, and the top layer verification environment module is used for reversely marking the SDF file to the BFM packaging module and running a test case. According to the method, the delay information of the BFM under each process corner is rapidly extracted by using the SDF generation component, the independent SDF file is generated and is reversely marked to the BFM packaging module, so that a real port time sequence can be simulated, multiple iterations are not needed, a large amount of manpower and time cost is saved, the delay information adding speed of the BFM is remarkably improved, and the error rate is reduced.

The invention provides a method and a system for testing and analyzing reliability of an integrated circuit under an extreme working condition, and relates to the technical field of testing. Identifying a limit working condition point under the critical state of the circuit function constraint condition; injecting random deviation to simulate circuit behaviors under different process corners to obtain reliability characteristic parameters; establishing a correlation model of a device degradation state and circuit function margin attenuation to predict life distribution; and determining a reliability level according to the life distribution and a preset threshold and generating a test report. The failure mode under the limit working condition can be accurately positioned, and the integrated circuit life prediction accuracy is improved.

An SRAM architecture is disclosed that provides a process- and temperature-compensated word-line underdrive scheme enabling stable, low-voltage operation. Each row decoder generates an initial word-line signal, derives an inverse word-line signal, and drives the corresponding word line through driver circuitry including a word-line underdrive p-channel transistor. The transistor's gate is controlled by the inverse word-line signal and optionally receives a dynamically generated negative bias to reduce device size while maintaining performance. Control circuitry includes a word-line underdrive sink circuit having dummy memory cells that replicate bit-cell behavior to generate a compensated driver output signal tracking process and temperature variations. A negative bump generator produces a transient below-ground potential at the gate node to enhance underdrive efficiency. This improves bit-cell stability, dynamic noise-margin yield, and performance uniformity across process corners and temperature, while minimizing silicon area.

This application provides a security monitoring method and a microprocessor architecture. The method is applied to a microprocessor architecture including a processor core and a security monitoring module. The security monitoring module includes a ring oscillator with adjustable inverter stages. The method includes: when the security monitoring module detects a change in the process corner of the ring oscillator, it adjusts the inverter stages of the ring oscillator according to the current process corner of the ring oscillator and the operating frequency of the monitored module, so that the operating frequency of the ring oscillator is consistent with the operating frequency of the monitored module. The monitored module includes any module in the microprocessor architecture, and the ring oscillator serves as a reference frequency source for security monitoring of the monitored module. The above method can provide a stable reference frequency within the microprocessor architecture, thereby improving the accuracy and effectiveness of security monitoring of the monitored module.

The invention provides an access control method and equipment of a storage circuit and a storage medium. The memory circuit is provided with a reading unit, also can be called a reading circuit, the reading unit is provided with an electric fuse, and the method comprises the following steps: setting a plurality of different reference resistance values for the reading unit; comparing the resistance value of the electric fuse with any reference resistance value; if the resistance value of the electric fuse is smaller than any reference resistance value, determining that the electric fuse is not burnt; and if the resistance value of the electric fuse is greater than any reference resistance value, determining that the electric fuse is burnt. On the basis, a plurality of reference resistance values used for reading the circuit are set, it is guaranteed that the reference resistance values cover the change range of the process corner, and therefore the product yield can be improved.

A process corner simulation system includes a frequency generator, a transistor sensitive circuit, and a process corner simulator. The frequency generator is used to generate a frequency signal. The transistor sensitive circuit is coupled to the frequency generator for receiving the frequency signal. The process corner simulator is coupled to the transistor sensitive circuit for receiving at least one output signal generated from the transistor sensitive circuit. The at least one output signal outputted from the transistor sensitive circuit includes speed information and duty cycle information. The process corner simulator uses a plurality of process corner models for generating a plurality of simulation results corresponding to different process corners according to the at least one output signal.

The invention belongs to the technical field of integrated circuits, and particularly relates to a positive temperature coefficient current generating circuit with process compensation. The circuit comprises a symmetric positive temperature coefficient current generating circuit or a complementary positive temperature coefficient current generating circuit. The symmetrical positive temperature coefficient current generation circuit comprises two positive temperature coefficient sub-current generation circuits; wherein one sub-current generating circuit comprises a positive temperature coefficient current biasing circuit with NMOS (N-channel metal oxide semiconductor) process characteristics, a first operational amplifier circuit and a first current mirror circuit; the other sub-current generating circuit comprises a positive temperature coefficient current biasing circuit with PMOS (P-channel Metal Oxide Semiconductor) process characteristics, a second operational amplifier circuit and a second current mirror circuit; the complementary positive temperature coefficient current generating circuit comprises a positive temperature coefficient current biasing circuit with dual-process characteristics, a third operational amplifier circuit and a third current mirror circuit; according to the invention, the asymmetry of a temperature curve caused by the asymmetry of a process corner can be effectively compensated while the positive temperature coefficient current is generated, so that the device has a good application prospect.

This application relates to a method, apparatus, processing equipment, and readable storage medium for processing corner connection speeds. The method includes: acquiring the corner constraint speeds of adjacent sub-processing trajectories; determining the local extrema of the corner constraint speeds based on the corner constraint speeds; and determining the planned corner connection speed of the sub-processing trajectories based on the corner constraint speeds, the local extrema of the corner constraint speeds, and speed planning model data of the sub-processing trajectories. The local extrema of the corner constraint speed is the speed of one endpoint of the sub-processing trajectory, and the planned corner connection speed is the speed of the other endpoint of the sub-processing trajectory. This method ensures that the speed of the other endpoint of the sub-processing trajectory is not too large or too small, and that the speeds of both endpoints of the sub-processing trajectory meet the requirements of the aforementioned speed planning model data. This prevents processing equipment (such as cutting equipment) from experiencing processing problems or incomplete processing (such as overcutting or undercutting) during actual processing, thereby improving processing quality.

Technologies and implementations for a voltage management circuit. The voltage management circuit may be configured to facilitate management of behavior of electronic devices including management of process corners associated with semiconductor integrated circuit devices. The technologies and implementations may facilitate a controlled amplitude for a signal that may be configured to push a negative ground capacitor. The amplitude may decrease as a process corner becomes faster.

The invention discloses a low-power-consumption reference source, which belongs to the technical field of integrated circuit design and comprises a current biasing circuit and a reference voltage generating circuit. The current bias circuit isolates fluctuation change of the power supply voltage while reducing the power supply voltage through a depletion type transistor, and outputs bias current; according to the reference voltage generation circuit, a parallel enhanced transistor which works in a sub-threshold region and adopts a hybrid bias mode is used as a load, and a reference voltage which is subjected to temperature compensation, low in power consumption and not changed along with temperature fluctuation is obtained according to a bias current. Besides, the method can be realized only through ingenious planning of body end connection on a layout level, additional process steps and manufacturing cost are not increased, a flexible and effective compensation dimension is provided for a designer, accurate optimization can be carried out aiming at a specific process corner and a working temperature range, and the method is suitable for large-scale production. And the practicability and the reliability of the reference voltage source in various high-performance analog and digital-analog hybrid integrated circuits are greatly improved.

The invention relates to a reference unit for an eFuse read module and a reference resistance setting method thereof, and aims at an eFuse adopting an AA fuse, the AA fuse uses a diffusion layer and a metal silicide layer thereof as a fuse medium, the AA fuse is different from fuses made of other materials, the AA fuse is mainly electromigration in the eFuse programming process, and the reference resistance of the AA fuse is set. The resistance values before and after fusing have normal distribution characteristics, the intermediate value of the resistance values before and after fusing of the AA fuse wire is used as the reference resistance value, and due to the fact that the state of the reference resistance value is the same as that of an actual fuse wire after fusing, the reference resistance value can be changed to the same degree under different process characteristics and temperatures, and therefore compared with a conventional fixed reference resistor, the resistance value of the AA fuse wire is greatly improved. According to the reference unit provided by the invention, the output deviation of a comparison circuit caused by the fact that a traditional fixed reference resistor cannot track changes is avoided, and the reading reliability of eFuse under various process corner and temperature conditions is greatly improved.

The present application relates to chip verification technical field, especially to a kind of front-end low-power verification environment generation method, electronic equipment and medium, method includes steps S1, the register transfer level code information A of chip is obtained n And unified power consumption format information B n ;Step S2, target configuration file is obtained;Step S3, the target configuration file is parsed, if C n It is set to first identification, then A1 n And B1 n Join target compilation file list, if C n It is set to second identification, then A2 n And B2 n Join target compilation file list;Step S4, at least one process angle corresponding standard cell library information file is screened from each standard cell library information file and joined target compilation file list;Step S5, based on the target compilation file list compiles and generates front-end low-power verification environment.The present application improves the generation efficiency and accuracy of front-end low-power verification environment.

The invention provides a low-power-consumption low-voltage detector, which relates to the technical field of detectors and comprises a detection branch, a bias branch and an output shaping module, the first end of the detection branch is connected with power supply voltage, the second end is connected with the bias branch, and the detection branch is used for outputting an overturning signal when the power supply voltage reaches set detection voltage; the bias branch is used for providing stable bias voltage for the detection branch and has a temperature compensation function; and the output shaping module is connected with the output end of the detection branch and is used for shaping the overturning signal and then outputting a detection signal. In the mode, ultralow detection voltage, ultralow power consumption, temperature stability, high process angle robustness and small chip area are realized, and the detection voltage is programmable.

The invention belongs to the field of radio frequency circuits, and particularly relates to a process angle self-adjusting circuit and method for controlling overshoot voltage existence duration, and the circuit comprises a judgment voltage generation circuit which is used for generating judgment voltage and outputting the judgment voltage to the positive input end of an upper limit comparator and the positive input end of a lower limit comparator; the window voltage generation circuit is used for generating a window voltage comprising an upper limit window voltage and a lower limit window voltage, outputting the upper limit window voltage to the negative input end of the upper limit comparator, and outputting the lower limit window voltage to the negative input end of the lower limit comparator; the upper limit comparator is used for comparing the judgment voltage with the upper limit window voltage and outputting a high level or a low level; and the lower limit comparator is used for comparing the judgment voltage with the lower limit window voltage and outputting a high level or a low level. By controlling the access number of the time control devices of the overshoot voltage generation module, the process corner control of the overshoot voltage on the existence time performance is successfully realized.

The invention provides a parameter processing method and device.The method comprises the steps that a circuit topological structure and a target manufacturing process under an original manufacturing process are obtained, and the circuit topological structure comprises circuit devices and the connection relation between the circuit devices; the target manufacturing process comprises N process corners of the circuit topological structure, M standard indexes and P candidate parameters of the circuit device; determining N1 representative process corners according to the N process corners; according to the circuit topological structure, the N1 representative process corners, the M1 standard indexes and the P1 candidate parameters, determining a target device parameter, 0 lt, meeting the target manufacturing process, of the circuit topological structure; m1 < = M, 0lt; p1 < = P. According to the method provided by the invention, the design parameter tuning work of the analog circuit device during process migration can be automatically completed, and the chip design quality and efficiency are improved.

This invention relates to the field of chip technology and discloses a chip screening method, apparatus, device, medium, and program product. The method includes: during the chip testing phase, acquiring process corner data corresponding to each initial chip; acquiring the target ambient temperature range and the target thermal design current upper limit; and, through a pre-established target correlation model between ambient temperature, process corner, and the target thermal design current upper limit, acquiring the process corner limitation range based on the target ambient temperature range and the target thermal design current upper limit; and, based on the process corner limitation range and the process corner data, screening out target chips from each initial chip. This method enables chip screening based on the thermal design current upper limit, reduces performance fluctuations between chips, and ensures the operating efficiency of the chip cluster.

The invention discloses a global process corner model, and in a global process corner model architecture, a global process corner of an electrical parameter of a semiconductor device is obtained by adding a TTG process corner of the electrical parameter to a standard deviation of the electrical parameter corrected by adopting an LOD correction function. The LOD correction function comprises an SA correction term, an SB correction term and a first constant term. The SA correction term is a correction term formed by multiplying a power function term of SA by a first channel parameter term. The SB correction term is a correction term formed by multiplying a power function term of the SB by a second channel parameter term. The first channel parameter item and the second channel parameter item have the same structure and at least comprise a second constant item, a power function item of L, a power function item of W and a ghost paper item of WL. Each has fitting parameters determined by fitting. The invention further discloses an extraction method of the global process corner model. According to the method, the fitting precision of the process corner model can be improved, the influence of the process change on the device performance can be reflected more accurately, and finally a more reasonable layout can be designed.

The embodiment of the invention relates to a simulation model, a generation method thereof, a simulation method, electronic equipment and a storage medium. The method comprises the steps that the position of a pseudo global process corner is determined based on the position of a preset global process corner and the correlation between target parameters of the global process corner, and the pseudo global process corner is used for assisting in defining the electrical property distribution range of a simulation object; process corner model parameters corresponding to the target parameters are adjusted based on the values of the target parameters at the positions of the global process corner and the pseudo-global process corner, so that the simulation values of the target parameters are consistent with the target values of the corresponding target parameters; and determining model parameters of the simulation model based on the adjusted process corner model parameters to generate the simulation model. According to the technical scheme, the accuracy of MC simulation can be improved.

A method for implementing timing closure of an ultra-large-scale SOC based on module division includes the following steps: S1, acquiring timing data of a full chipset, and dividing an SOC into three modules; S2, reading lib, lef, netlist and def in each module, determining each specific module requiring timing recovery and each prototype module not requiring timing recovery, reading lib and lef in each specific module, and reading netlist and def in each prototype module; S3, creating multiple process corners and acquiring timing data of each process corner, and back-annotating and reading netlist and def out of the multiple process corners corresponding to each specific module to determine an attribute-maintained part and a to-be-recovered part; and setting the attribute-maintained part and each prototype module to be in a not-to-be-recovered state; and S4, sending out a timing recovery command, and performing timing violation fixing on the to-be-recovered part.

The disclosed embodiments provide a DLL delay chain adjustment method and system, comprising: obtaining an external clock signal and a feedback clock signal, and determining a clock phase difference signal based on the external clock signal and the feedback clock signal; obtaining actual temperature and voltage information of the DLL at a target sampling time, as well as actual process corner level information of the DRAM; determining a target step size control signal based on the actual temperature, voltage, and process corner level information; and determining a target control signal for an adjustable delay chain based on the clock phase difference signal and the target step size control signal, thereby controlling the adjustable delay chain using the target control signal. This prevents the DLL's adjustable delay chain from being recalibrated if a significant deviation between the internal clock and the external clock is subsequently caused by external factors such as PVT, thereby preventing normal read or write operations of the DRAM from being performed.

The invention belongs to the technical field of analog integrated circuits, and particularly relates to an ultralow-temperature-drift band-gap reference circuit which comprises a first-order band-gap reference circuit and a high-order temperature compensation circuit. The first-order band-gap reference circuit comprises a starting circuit, a band-gap reference core circuit and an output zero-temperature current circuit; the starting circuit is connected with the band-gap reference core circuit and the output zero-temperature current circuit, the band-gap reference core circuit is connected with the output zero-temperature current circuit, the output zero-temperature current circuit is connected with the high-order temperature compensation circuit, and the high-order temperature compensation circuit is connected with the band-gap reference core circuit; according to the high-order temperature compensation circuit, the full temperature section is divided into four sections, the high-order compensation current is generated by adopting the tube working in the sub-threshold region, and the compensation current in the high-temperature section and the leakage current of the triode are superposed to weaken the temperature drift coefficient, so that the compensation current in the high-temperature section is extracted, the temperature drift coefficient is optimized, and the temperature drift coefficient is reduced. The ultra-low temperature drift performance of the whole process corner is achieved, and the circuit stability and the environmental adaptability are improved.

A circuit for controlling calibration includes a process circuit, an off-chip calibration circuit and a mode switching circuit. The process circuit is configured to perform, in a first test mode, a process corner test on the memory to obtain a test result signal, the test result signal being used for determining a process corner parameter. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a controller, the first calibration code being determined by the controller according to a current environment parameter of the memory and the process corner parameter.

The invention provides a time sequence violation repairing method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, and the method comprises the steps: after obtaining a violation path set of an integrated circuit under a plurality of process corners, selecting one process corner from the plurality of process corners as a reference process corner, and taking the other process corners as non-reference process corners, and taking the violation path set of the reference process corner and the violation path set of each non-reference process corner as a target violation path set, performing static time sequence analysis on time sequence violation paths in the target violation path set according to the reference process corner, and performing time sequence violation repair according to an obtained target time sequence analysis report. According to the method, on the basis of the violation path set of the reference process corner and the unique time sequence violation paths in the violation path set of other non-reference process corners, the obtained target violation path set does not have repeated time sequence violation paths, so that a large amount of repeated work can be avoided, the data volume of time sequence violation repair is effectively reduced, and the time sequence violation efficiency is improved.

The application belongs to the field of radio frequency circuits, and particularly relates to a process angle self-adjusting circuit and method for controlling the duration of an overshoot voltage, comprising: a decision voltage generation circuit, configured to generate a decision voltage and output the decision voltage to the positive input terminals of an upper limit comparator and a lower limit comparator; a window voltage generation circuit, configured to generate a window voltage comprising an upper limit window voltage and a lower limit window voltage, output the upper limit window voltage to the negative input terminal of the upper limit comparator, and output the lower limit window voltage to the negative input terminal of the lower limit comparator; the upper limit comparator, configured to compare the decision voltage and the upper limit window voltage and output a high level or a low level; and the lower limit comparator, configured to compare the decision voltage and the lower limit window voltage and output a high level or a low level. The application successfully realizes process angle control over the existing time performance of an overshoot voltage by controlling the access number of time control devices of an overshoot voltage generation module.

The present disclosure provides a transistor process corner detection method, device and electronic equipment, which is applied to the field of integrated circuit manufacturing technology. The transistor process corner detection method is realized by a ring oscillator composed of a transistor to be detected, the transistor to be detected including a P-type transistor and an N-type transistor, and the method includes: obtaining an oscillation period of an output signal of the ring oscillator; obtaining an amplitude average value of the output signal of the ring oscillator; determining a process corner of the N-type transistor and the P-type transistor in the ring oscillator according to a ratio of the amplitude average value to a power supply voltage of the ring oscillator and a comparison result of the oscillation period with a first threshold value and a second threshold value, wherein the first threshold value is greater than the second threshold value. The embodiment of the present disclosure can improve the speed of detecting the transistor process corner.

The application relates to the chip design technical field, in particular to a method for optimizing generation of a gate-level netlist. The method comprises the following steps: obtaining a standard cell library file and a user configuration file; obtaining preset performance parameter information of each standard cell of each standard cell type to be evaluated under each process angle to be evaluated according to the standard cell library file and the user configuration file; obtaining a comprehensive performance value of each standard cell under a process angle combination to be evaluated according to the preset performance parameter information and evaluation weights of the preset performance parameters; generating a standard cell disabling list according to the comprehensive performance value; converting the standard cell disabling list into a constraint script of a comprehensive tool, and loading the constraint script into a comprehensive environment as a hard constraint, so that the standard cells in the standard cell disabling list are avoided by the comprehensive tool in the process of mapping RTL (Register Transfer Level) code to the gate-level netlist. The application can solve the problems of low chip design efficiency and high cost.

The application discloses a voltage control system, which comprises a power management integrated circuit (PMIC), a dynamic random access memory (DRAM) and a register clock driver (RCD). The RCD is electrically connected with the DRAM and the PMIC respectively. When the DRAM is running, the RCD acquires process corner information of the DRAM, and controls the PMIC to adjust the working voltage of the RCD based on the process corner information. The application acquires the process corner information of the DRAM through the RCD, controls the PMIC to adjust the working voltage of the RCD through the process corner information, accelerates the circuit switching speed in the RCD through the improved working voltage, improves the device switching speed of the transistor in the DRAM under the SS process corner, reduces the system delay, thereby compensating the speed deficiency problem caused by the process, and improving the data transmission speed of the DRAM.

A novel bandgap reference startup circuit with degeneracy state detection is disclosed, particularly relating to the design of integrated circuit power control chips. The circuit includes a novel bandgap reference startup circuit and a bias voltage and enable signal generation circuit. The novel bandgap reference startup circuit comprises a startup circuit and an inverter, a degeneracy-removal current generation circuit, a bandgap core and process corner adaptive compensation circuit, and a Schmitt trigger circuit. This invention utilizes the on / off characteristics of MOSFETs to achieve startup. By detecting the difference in degeneracy state between the core devices of the second-order compensated bandgap circuit (such as BJTs and MOSFETs) at the degeneracy point and in normal operating conditions, it can accurately identify and effectively remove the bandgap reference circuit from the degeneracy state. Simultaneously, it adapts to the spurious operating point detection requirements of first-order bandgap circuits, accurately identifying the operating state of the reference circuit and effectively solving problems such as unreliable startup, high power consumption, inaccurate judgment, and poor adaptability in existing circuits.

The application discloses a kind of reference current source circuit, including reference current generation module, band gap reference module, process angle detection module and current compensation module.Reference current generation module is used to generate a reference current, the reference current changes with process angle deviation, band gap reference module is used to generate a band gap reference voltage with different voltage values under different process angles, process angle detection module is used to compare the band gap reference voltage with at least one reference voltage, and generate detection signal according to the comparison result, current compensation module is used to provide corresponding compensation current to the reference current generation module according to the detection signal, to compensate the reference current, so that the reference current output by circuit can be substantially consistent under typical process angle TT, slow process angle SS and fast process angle FF, and the reference current not affected by process angle deviation is obtained.