The application belongs to the technical field of low
power consumption, and particularly relates to a low
power consumption design method and device with adaptive
voltage regulation. The method comprises the following steps: 1) simulating a key path of an analog-digital circuit, wherein the key path refers to a path with the maximum
delay in the digital circuit; 2) generating a test
clock signal and a sampling
clock signal, and inputting the generated test
clock signal into the key path; 3) detecting the output signal of the key path by using the sampling
clock signal with the same sampling time and / or different sampling times, and controlling and adjusting the
power supply voltage of the digital circuit according to the detection result, so as to determine the minimum
power consumption voltage for ensuring the normal operation of the digital circuit. The application uses the key path to represent a complex load, and has simple structure and wide application range. The
power supply voltage of the circuit is controlled and adjusted according to the
voltage detection result, so that the control precision and the adjustment efficiency are improved, the minimum voltage for ensuring the normal operation of the circuit is determined, and energy saving is achieved.