7 results about "Adaptive voltage scaling" patented technology

The application belongs to the technical field of low power consumption, and particularly relates to a low power consumption design method and device with adaptive voltage regulation. The method comprises the following steps: 1) simulating a key path of an analog-digital circuit, wherein the key path refers to a path with the maximum delay in the digital circuit; 2) generating a test clock signal and a sampling clock signal, and inputting the generated test clock signal into the key path; 3) detecting the output signal of the key path by using the sampling clock signal with the same sampling time and / or different sampling times, and controlling and adjusting the power supply voltage of the digital circuit according to the detection result, so as to determine the minimum power consumption voltage for ensuring the normal operation of the digital circuit. The application uses the key path to represent a complex load, and has simple structure and wide application range. The power supply voltage of the circuit is controlled and adjusted according to the voltage detection result, so that the control precision and the adjustment efficiency are improved, the minimum voltage for ensuring the normal operation of the circuit is determined, and energy saving is achieved.

Integrated circuits on semiconductor substrates and methods for operating integrated circuits on semiconductor substrates. The method includes adjusting a clock signal, generated by a clock circuit, from a first frequency to a second frequency. The method also includes adjusting a digital supply voltage, generated by a digital supply voltage converter, to a predetermined maximum value for the second frequency. The method further includes adjusting a body biasing voltage, generated by a body voltage converter, to a predetermined value for the second frequency. The method also includes determining, by a controller, speed margins based on logic speed measurements from a logic gate delay line. The method further includes decreasing the digital supply voltage until the speed margins are less than a predetermined threshold margin. The clock circuit, the digital supply voltage converter, the body voltage converter, the controller, and the logic gate delay line are implemented on the semiconductor substrate.

A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

An Adaptive Voltage Scaling (AVS) system, method and apparatus, and a device. The system includes at least two controllers, a switching module, and a control object. The switching module is connected to the controllers through a bus, an output end of the switching module is connected to an input end of the control object, and the switching module scales the control object through AVS; and the switching module scales the occupied state of the bus through a selected controller, whereby the selected controller scales the control object through the bus.

A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.

A versatile adaptive voltage scaling control circuit, related apparatus, and related method are provided. A method includes monitoring one or more parameters determined to be associated with performance of a device that is driven by a direct current-to-direct current (DC-DC) converter. The method also includes determining a voltage target based on the one or more parameters and comparing the voltage target to a power supply voltage. Further, the method includes selectively adjusting an output voltage of the DC-DC converter via a feedback loop based on a result of the comparing.

An Integrated Circuit (IC) includes electronic circuitry, multiple sensors, and an Adaptive Voltage Scaling (AVS) circuit. The electronic circuitry is configured to be powered by one or more supply voltages. The multiple sensors are configured to measure values affected by the one or more supply voltages, and to produce multiple sensor outputs. The AVS circuit is configured to adaptively set the one or more supply voltages by applying to the sensor outputs an AVS model having one or more user-defined parameters, to generate performance data based on the sensor outputs, to export the performance data from the IC, to receive the one or more user-defined parameters into the IC in response to the performance data, and to configure the AVS model to operate in accordance with the received user-defined parameters.