59 results about "Adaptive voltage scaling" patented technology

There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.

Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.

A system and method for slack determination in a logic integrated circuit. A launch pulse is input to a circular delay loop circuit. The leading edge of the launch pulse causes a pulse to circulate around the circular delay loop. The number of passes made through the loop by the circulating pulse is counted by a latch/counter circuit. A sample pulse is input to the latch/counter circuit to latch the number of pulse circulations at the leading edge of the sample pulse. The pulse circulation count provides delay information in the circuit that may subsequently be used to adjust a supply voltage in the integrated circuit.

Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.

A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of clock domains. Each hardware performance monitor is associated with one of the plurality of clock domains and provides a signal that measures a performance of its respective clock domain temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and used in an advanced power controller to provide adaptive voltage scaling for the integrated circuit system.

A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the adaptive voltage scaling (AVS) system. The present invention provides multi-point calibration by calibrating a Reference Calibration Code (RCC) for each operating point (clock frequency) of the adaptive voltage scaling (AVS) system.

Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.

The invention discloses a delay sampling circuit having self-calibration function. The delay sampling circuit includes a pulse generation circuit, a replication path unit, a calibration delay circuit, an edge sampling circuit, and a delay sampling control module, wherein, the replication path unit is in a variable voltage area, and other parts are in a fixed voltage area. The invention can be applied to reflect a time sequence condition of a chip and to guide voltage scaling of the chip. Two operation modes of a self-calibration mode and an adaptive voltage scaling mode are provided according to the delay sampling circuit, and cooperate with adaptive voltage scaling to operate together, which can prevent measurement deviation of the chip that results from environment change during operation, thus simultaneously giving consideration to real-time performance and reliability, and can allow the monitored circuit to operate in the required lowest voltage, thus reducing power consumption of the circuit effectively.

A semi-adaptive voltage scaling method and device for determining minimal supply voltages for digital electronic semiconductor circuitry, e.g., microprocessors, of electronic devices under production testing and “real” operating conditions. The SAVS operates in a closed-loop during a production test phase of the circuitry and in an open-loop mode in an application (operation) phase of the semiconductor circuitry. During production testing, a lowermost level of the supply voltage for the semiconductor circuitry is determined at one single defined temperature at which operating specifications of the circuit are met. The lowermost level is stored in a dedicated electronic memory of the circuitry together with temperature dependent parameters. Afterwards, when the digital electronic circuitry is operated in a “real” application, e.g., a mobile phone, the device and method reads the previously measured and proven data from the memory and regenerates the minimum level of supply voltage for the circuitry, taking into account the actual temperature of the application. As a result, the digital semiconductor circuitry in the “real” application is supplied with a minimum level of supply voltage, whereby specified parameters of the circuitry are met. Thus, a power consumption of the circuitry is advantageously reduced to a minimum.

A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.

A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of threshold voltage V_T logic libraries. Each hardware performance monitor is associated with one of the plurality of threshold voltage V_T logic libraries and provides a signal that measures a performance of its respective threshold voltage V_T logic library die temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and provided to an advanced power controller for use in providing adaptive voltage scaling for the integrated circuit system.

AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.

There is disclosed clock control circuitry for selectively applying a clock signal to a digital processing component wherein the clock signal is capable of being changed to a plurality of operating frequencies. The clock control circuitry is operable to (i) receive a command to change a first operating frequency to a second operating frequency, (ii) in response to the command, disable the applied clock signal, (iii) generate a test clock signal having the second operating frequency, (iv) apply the test clock signal to a power supply adjustment circuit, and (v) sense a status signal from the power supply adjustment circuit. The status signal indicates that a power supply level of the digital processing component has been adjusted to an optimum value suitable for the second operating frequency.

Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.

There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.

A system and method is disclosed for rapidly increasing a rising slew rate of an adjustable power supply signal in an adaptive voltage scaling system. When a central processing unit of an adaptive voltage scaling system requests an increase in a performance level, a closed loop control mode of the adaptive voltage scaling system is disabled. Then a value of voltage that corresponds to the requested increased performance level is provided as a voltage change command to an adaptive voltage scaling regulator. The adaptive voltage scaling system is then operated at a maximum slew rate that can be achieved by the adaptive voltage scaling regulator. The closed loop mode is enabled after the adjustable power supply voltage reaches the requested voltage value.

A method, digital circuit, and computer program product control a supply voltage of a processing circuit based on a processing clock of the processing circuit. A first clock frequency and at least one second clock frequency are generated, wherein the first clock frequency is used as the processing clock and the second clock frequency is adjusted based on a clock control information issued by the processing circuit. A voltage conversion ratio for converting the supply voltage to a scaled supply voltage applied to the processing circuit is directly controlled in response to the result of a monitored performance under said second clock frequency. Thereby, a new fast automatic voltage scaling approach can be provided which allows to meet critical timing requirements of portable systems and to reduce power consumption significantly.

An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided.

The represent invention relates to a design process optimization system and method for designing a circuit which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed, and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit.

The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.