The invention belongs to the field of integrated circuits, and particularly relates to a 9T-SRAM unit, a
floating point memory computing circuit and a CIM
chip. In the 9T-SRAM unit, P1, P2 and N1-N4 form a latch structure with inverted storage nodes Q and QB; the grid
electrode of the N6 is connected with the Q; the source
electrode of the N6 is connected with the VSS; the drain
electrode of the N6 is connected with the source electrode of the N5; the grid electrode of the N5 is used as an input port INPUT of multiplication; the grid electrode of the P3 is connected with a switch
signal line KEY; drain electrodes of the N5 and the P3 are connected and serve as an output port OUT of a multiplication result. The
floating point in-memory calculation circuit comprises a memory calculation array, a finger
tail precision mapper, a sensitive
amplifier array and a shift
adder. The storage array is formed by arranging a 9T-SRAM unit array; and the finger
tail precision mapper is used for converting the input index difference value into a multi-bit precision
mask for controlling the starting state of each column of the storage and calculation array, and carrying out bit-by-bit adjustment on the precision
mask in a subsequent period. According to the invention, the problems of high
power consumption and large area commonly existing in the existing
floating point memory calculation can be solved.