483 results about "Power manager" patented technology

An improvement in a real time operating system for supporting at least one application, a processor and at least one hardware resource. The operating system includes a power manager layer. Such power manager layer is arranged to exchange information with an application, the processor and at least one hardware resource to provide real time power management responsive to the information.

A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

A system for rack level power management, the system comprising: at least one power source; a management module; and a plurality of power managed modules in communication with the management module and connected to draw power from the at least one power source, each of the plurality of power managed modules comprising a power manager and an operating circuit, the operating circuit being operable at a plurality of power drawing levels responsive to the power manager, the management module being operative to allocate a power budget to each of the plurality of power managed modules and communicate the allocated power budgets to the power managers, each of the power managers being operative to control the operating circuit of the power managed module to be operable at a power drawing level within the allocated budget.

A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

Various aspects of invention provide portable power manager operating methods. One aspect of the invention provides a method for operating a power manager having a plurality of device ports for connecting with external power devices and a power bus for connecting with each device port. The method includes: disconnecting each device port from the power bus when no external power device is connected to the device port; accessing information from newly connected external power devices; determining if the newly connected external power devices can be connected to the power bus without power conversion; if not, determining if the newly connected external power devices can be connected to the power bus over an available power converter; and if so, configuring the available power converter for suitable power conversion.

A system and method for Quality of Service (QoS) based server cluster power management is disclosed. The method of the present invention includes: grouping activities within a server cluster into predefined sets; assigning a priority level to each set; identifying a server hosting a set of lower-priority activities within the cluster; receiving a power interruption signal; and diverting power reserves of the server to another server in the cluster, in response to the power interruption signal. The system of the present invention includes: servers, hosting a plurality of activity sets each having an associated QoS level; power reserves coupled to the servers; a switch matrix coupled to direct the power reserves between the servers; and a power manager, coupled to the switch matrix, for commanding the switch matrix to divert power from servers hosting low QoS activity sets to servers hosting high-priority activity sets, in response to a power interruption.

Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.

The present invention discloses a PFC-PWM controller having interleaved switching. A PFC stage generates a PFC signal for switching a PFC boost converter of a power converter. A PWM stage generates a PWM signal for switching a DC-to-DC converter of the power converter. The PFC-PWM controller includes a power manager for generating a discharge current and a burst-signal. Under light-load conditions, the discharge current decreases in proportion to a load of the power converter. The burst signal is utilized to disable the PFC signal in a suspended condition for power saving. A pulse width of the pulse-signal ensures a dead time to spread switching signals, such as the PFC and PWM signals, and reduces switching noise. When the discharge current decreases, the pulse width of the pulse-signal will increase and a frequency of the pulse-signal will decrease correspondingly. This further reduces power consumption under light-load and zero-load conditions.

The invention is directed towards minimizing power consumption in computer systems. One embodiment of the invention is a power management system that is used for a computer system that has at least one device and one power domain. This embodiment uses two different power managers to manage the power consumption of the device and the power domain. Specifically, this embodiment has (1) a first power manager that determines when to change power state of the device, and (2) a second power manager that determines when to change power state of the power domain. Each of these power managers decides to change the power state of its corresponding device or domain based on information from several different sources. These sources can include power-management clients and power managers of related domains or devices.

A power manager is configured to manage power for a battery-powered application. A power source, a load and a battery are interconnected through a circuit path. Power from the power source is provided to the load and battery by a switching regulator. Various implementations are presented.

Various aspects of the invention provide power manager enclosures. One aspect of the invention provides a power manager enclosure including: a sealed housing comprising opposing substantially rectangular top and bottom faces, opposing substantially rectangular longitudinal front and back faces and opposing substantially rectangular transverse left and right side faces; and a plurality of device ports for operably connecting external power devices to the power manger disposed on one or more of the left and right side faces and on only one of the front and back faces.

Methods, systems, and computer program products are disclosed for controlling the allocation of power to a plurality of computers whose supply of power is managed by a common power manager by assigning by a workload manager a power priority to each computer in dependence upon application priorities of computer software applications assigned for execution to the computer and providing, by the workload manager to the power manager, the power priorities of the computers. Controlling the allocation of power to a plurality of computers whose supply of power is managed by a common power manager may include allocating by the power manager power to the computers in dependence upon the power priorities of the computers.

A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.

Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate. The voltage value, frequency value, and unique pointer of a given pstate definition are configurable, during operation of the data processing system, by the power manager module in response to changes in the operating parameters of the data processing system.

In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors.

Information handling system power management in standby and hibernate states is adapted to reduce transition times for end user requests to resume to an operational state. During fast resume time periods, transitions to the hibernate state are limited so that recovery to an operational states has the reduced resume time associated with the standby state. The fast resume time periods are set by user preference or automatically set by monitoring end user interactions with the information handling system to predict fast resume times appropriate for the end user. In one embodiment, a power manager automatically transitions the information handling system from the hibernate state to a standby state a predetermined time period before a fast resume period begins.

Power from a modular chassis to plural modular information handling systems contained by the chassis is dynamically allocated according to power consumed at each modular information handling system and a priority associated with each modular information handling system. A power manager of the modular chassis allocates power by setting a maximum power for each modular information handling system based upon a priority for each modular information handling system. A power monitor on a modular information handling system requests additional power allocation if power consumed is within a predetermined amount of the maximum power for that system. The power manager allocates additional power in response to the request if another modular information handling system has excess power allocated or if the requesting modular information handling system has a higher priority than another modular information handling system. The requesting system's maximum power is increased and the other system maximum power is decreased so that the maximum power available from the chassis is not exceeded.

Power down to a reduced power state, such as a standby or off state, of an information handling system is delayed by a user-configured time after detection of closing of the cover of the information handling system. In one embodiment, a cover delay module associated with the BIOS of the information handling system delays communication of the detection of the closing of the cover from the BIOS to a power manager of the operating system that commands the reduced power state. In another embodiment, the cover delay module integrates with the operating system power manager.

The invention broadly encompasses a system including a communications network, a plurality of remotely located data sources to provide power data, the power data including quantitative and qualitative data of one or more renewable energy power generation units, and a performance monitor in communication with the plurality of remotely located data sources through the communications network, the performance monitor including a data store to store the power data, and a power manager to manage generation of power from the one or more renewable energy power generation units.

Power is supplied to electrical devices while priorities between the electrical devices are being changed according to the states of use by a user instead of predetermined fixed priorities between the electrical devices, supply of power from a commercial power source can be controlled in real time at a request for power required by the user, and supply of power meeting QoL required in user's daily life is controlled. A power manager determines power to be assigned to each electrical device by inquiring a home appliance agent of whether or not the electrical device is capable of adjusting an operating function mode set as a target of a service operation of the electrical device, and of power for the electrical device. If the electrical device is capable of adjusting the operating function mode, the power manager obtains as a power assignment message the operating function mode set as a target for the electrical device and/or a power mode with power necessary for reaching the operating function mode as a target and with necessary time. If the electrical device is not capable of adjusting the operating function mode, the power manager obtains a power mode as a power assignment message without considering the operating function mode. The power manager includes a memory for transmitting the obtained power assignment message to the home appliance agent.