35 results about "Power manager" patented technology

The invention discloses a power management system adapted to an extremely low temperature environment. Through a multi-level self-adaptive heating mechanism and a hardware-algorithm cooperative control strategy, stable operation in an extremely low temperature environment is realized. The power manager integrates a closed-loop temperature control system and double-order starting logic of'hardware priority-software takeover ', the special charger adopts a distributed temperature sensing and space temperature field reconstruction technology, reliable charging and discharging management under the extreme environment of-68 DEG C is achieved through cooperation of the closed-loop temperature control system and the space temperature field reconstruction technology, heating extra power consumption is reduced by 90% or above, and the maximum temperature difference of a battery bin is smaller than or equal to 2 DEG C; and the cold start success rate is 100%. The power supply system can be widely applied to extremely-low-temperature individual power supply systems, extremely-low-temperature battery packs and other scenes, and the core technical bottleneck of the power supply system in an extreme environment is solved.

A power management system with differentiated power scaling including multiple activity monitors and a differentiated power manager. Each activity monitor counts performance benefit estimation events of each of multiple devices to determine performance benefit estimate values, each being a measure of relative power utilization efficiency of a corresponding device. The differentiated power manager periodically evaluates the performance benefit estimate values and dynamically adjusts relative power provided to each device to achieve differentiated power scaling based on the performance benefit estimate values. Additional power available during a higher performance mode may be distributed only to those devices with higher performance benefit estimate values. During any mode of operation, the power provided to those devices with lower performance benefit estimate values may be redirected to those devices with higher performance benefit estimate values. Power may thus be distributed in an unequal manner to benefit those devices operating at higher efficiency.

This invention relates to the field of door lock charging technology, specifically a door lock system and method with wireless charging functionality. The system includes a door frame, a door panel, a door lock, an AC-DC conversion module, a battery module, and an AC-DC rectifier and filter module. The AC-DC conversion module is concealed within the inner side of the door frame and is integrated with an inverter circuit and a resonant circuit. The inverter circuit is connected to an external constant-current input circuit via a wire guide. The AC-DC rectifier and filter module is concealed within the side of the door panel and is mainly integrated with a receiving coil, a processing chip, and a capacitor. The battery module is also concealed within the side of the door panel and mainly consists of a power manager and a battery. This invention, through the extension of wireless charging technology, modifies the door frame and door panel structure, enabling wireless charging between the AC-DC conversion module on the door frame and the AC-DC rectifier and filter module on the door panel when the door is closed, thereby achieving real-time charging of the battery within the door panel.

An apparatus and method for efficiently managing performance and power consumption between replicated functional blocks of an integrated circuit despite circuit behavior differences between these functional blocks due to manufacturing variations. In one embodiment, an integrated circuit includes a plurality of replicated functional blocks, each of which is a semiconductor die having a corresponding communication structure for routing packets. A second functional block placed between the first functional block and the third functional block routes packets to destinations from at least the first functional block and the third functional block, and provides higher performance than the first functional block and the third functional block due to semiconductor manufacturing variations. The power manager allocates a single supply voltage to the replicated functional blocks and allocates a target clock frequency to the first functional block and the third functional block. The power manager allocates another clock frequency greater than the target clock frequency to the second functional block.

The invention provides a power consumption adjusting and reducing device and a power consumption adjusting and reducing method. The power consumption adjusting and reducing device comprises a first master controller, a processor and a power manager, the power manager includes a model acceleration algorithm. The first master controller is used for outputting a first active transmission signal. The model acceleration algorithm is used for controlling a clock source of the processor or a power supply of the processor according to the first active transmission signal to reduce power consumption of the processor.

An embodiment includes detecting by a resource module of a disaster recovery system of a datacenter a resource metric. The embodiment includes responsive to the resource metric, computing a priority score by a priority scoring module of the disaster recovery system based on the resource metric. The embodiment includes predicting, by a prediction module of the disaster recovery system, a predicted resource usage metric based in part on the resource metric. The embodiment also includes powering on a node of the datacenter by a power manager module of the disaster recovery system based on the priority score and the predicted resource usage metric.

An apparatus includes a housing. The housing has an interface portion configured to complementarily fit with an interface portion of an appliance. The apparatus includes a communication interface configured to be removably coupled with the appliance. The apparatus includes a power interface configured to be removably coupled with the appliance. The apparatus includes a processor configured to identify an appliance type of the appliance based on appliance communications and generate a signal based on the appliance type. The apparatus includes an AC interface configured to be coupled with an AC grid. The apparatus includes a battery. The apparatus includes a multi-mode inverter configured to receive power from the AC grid and / or the battery and send power to the appliance, based on the signal. The communication interface, the power interface, the processor, the AC interface, the battery, and the multi-mode inverter are each at least partially disposed in the housing.

An apparatus and method for efficiently managing power consumption of multiple partitions of an integrated circuit. A processing unit includes multiple partitions, each assigned to operation parameters of a respective power domain. Each of the partitions is assigned to operating parameters of a respective power domain. A power manager accesses a total power consumption budget for the multiple partitions and sends corresponding assigned power limits to the multiple partitions. A particular partition calculates a corresponding measurement of power consumption as a weighted sum of sampled signals, and performs steps to reduce power consumption when the particular partition determines the corresponding measurement of power consumption exceeds a corresponding assigned power limit. The power manager updates the assigned power limits within a first time interval. The multiple partitions calculate the power consumption measurements and perform power reduction steps within a second time interval less than the first time interval.

The present invention relates to a power control system and a system-on-chip device including the same, which controls power of a plurality of power domains constituting the system-on-chip device by performing power control decisions at a software level and power control execution at a hardware level in parallel. The power control system according to the present invention includes a central processor configured to make decisions on power-up or power-down of at least one target power domain among a plurality of power domains included in the system-on-chip device, and transmit at least one domain power control command among a domain power-up command and a domain power-down command based on the domain power-up / power-down decisions, and a domain power manager configured to receive the domain power control command and execute at least one of a power-up sequence and a power-down sequence for the target power domain.

Disclosed are a system and method for designing a power management controller that performs power control of a plurality of power domains in a system-on-chip (SoC) device using a no-code approach. The system comprises a memory configured to store instructions and a processor configured to execute the instructions. The instructions include operations for generating a root power manager instance based on a root power manager component, generating at least one domain power manager instance based on one or more domain power manager components, establishing connections between output ports of the root power manager instance and input ports of the domain power manager instances, allocating memory storage space for each power manager instance, and generating hardware code of power elements, register code corresponding to the power elements, hardware code corresponding to ports and connections, and binary code corresponding to an operation sequence of the power management controller.

The application discloses a protection circuit, a protection method and an electronic device, relates to the electronic field, and is used for preventing new features of a protected chip from being reverse deciphered. The protection circuit is arranged in an electronic device, and the electronic device comprises a mainboard and a shell. The protection circuit comprises an antenna, a radio frequency circuit, a protected chip, a power manager, a first antenna interface, a second antenna interface and a processor. The antenna and the first antenna interface are arranged on the shell. The radio frequency circuit, the protected chip, the power manager, the second antenna interface and the processor are arranged on the mainboard. The first antenna interface is connected with the antenna. The second antenna interface is connected with the radio frequency circuit. The processor is used for: acquiring, from the radio frequency circuit, a strength value of a radio frequency signal of the second antenna interface received by the first antenna interface; and in the case that the strength value is a first value representing that the first antenna interface and the second antenna interface are in a disconnected state, controlling the protected chip to be powered off by the power manager.

An inverter (200) is disclosed, which is connected to an energy source (100) and configured to supply power to a load network (300) comprising at least one controllable load, the inverter (200) comprising a processor (201) for controlling the at least one controllable load of the load network (300). The processor (201) comprises a net load detector (201a) which detects a net load of the load network (300), a power output analyzer (201b) which determines an inverter power delivery of the inverter and a grid power delivery of a grid (400), characterized by a power manager (201c) which changes a power output of the inverter (200) and a power consumption of the at least one controllable load based on the inverter power delivery, the grid power delivery, an output condition violation and a derating state of the energy source (100).

A power manager of an apparatus exposes an application programming interface (API) usable for applications to specify priority and quality-of-service (QoS) parameters (e.g., bandwidth requirements) for a workload. An application, for instance, specifies the priority and QoS parameters for a workload to be processed using a hardware compute unit. The power manager employs the priority and QoS parameters to configure the bandwidth allocation to access a memory system. In particular, the bandwidth allocation and prioritization are dynamically extended to real-time and best-effort workloads to satisfy specified QoS parameters for inference workloads and improve user experiences.

The presently disclosed technology provides methods and systems for optimally allocating power among workloads executing on a computer system through use of a power management algorithm. For example, according to the present technology a plurality of CPUs within a server can be divided into multiple groups according to application workloads. Workloads can be distributed to the CPUs as needed by a workload scheduler, and the workload scheduler can provide the CPU IDs to a power manager, enabling the power manager to optimize power settings. Each group of CPUs can be assigned an optimal power profile tailored to its respective situation.

The electronic device includes: a display panel including pixels; a panel driver configured to drive the display panel in response to the energization signal; and a power manager configured to apply a power voltage to the panel driver in response to a power voltage start signal, in which the panel driver includes a voltage generator configured to output a first power voltage to the display panel based on the power voltage, in which the voltage generator and the power manager are connected through a voltage line, wherein the voltage generator is configured to output a droop voltage to the voltage line in response to the voltage droop start signal, and wherein the voltage generator is configured to output the droop voltage to the voltage line based on the power voltage output to the voltage line.

An engine. A movable member is coupled to an output shaft and displaced responsive to a magnetic field that causes rotation of the output shaft. A plurality of replaceable cartridge modules each comprises a plurality of coils for generating the magnetic field when energized. Each cartridge also includes a moveable member. A sensor is configured to provide an output shaft angle. A timing controller is configured to energize each coil within each one of the plurality of cartridge modules; the energization responsive to one or both of the output shaft angle and an external load. Energizing each coil generates the magnetic field at predetermined angular positions of the output shaft. A generator or alternator mechanically coupled to the output shaft generates an electrical output. A power manager partitions the electrical output among an energy storage device, an external load, and energization of the plurality of coils.

A power reduction device includes a first master controller, a processor, and a power manager. The power manager includes a model acceleration algorithm. The first master controller is configured to output a first active transmission signal. The model acceleration algorithm is configured to control the clock source of the processor or the power supply of the processor to reduce the power consumption of the processor according to the first active transmission signal.

Provided in the present application is a display apparatus. A first drive transistor in a pixel circuit of the display apparatus is electrically connected to a first data writing transistor, wherein one of a source electrode and a drain electrode of the first drive transistor is connected to a light-emitting element, and the other one is electrically connected to a power manager, the power manager being used for sequentially outputting, on the basis of a first enable signal, a first voltage sub-signal and a second voltage sub-signal to the other one of the source electrode and the drain electrode of the first drive transistor in a first time period and a second time period.

1. Name of the product in this design: Power Manager (VP Ext). 2. Purpose of this design: A device for managing controllable power supplies. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The invention relates to a system and a method for designing a power management controller in a code-free manner. The system comprises a memory for storing at least one instruction; and at least one processor to execute the at least one instruction stored in the memory. The at least one instruction includes instructions to generate a root power manager instance based on a root power manager component, a domain power manager instance based on a domain power manager component; instructions to set a connection between an output port of the root power manager instance and an input port of the at least one domain power manager instance; instructions to respectively allocate memory storage space to power manager instances constituting the power management controller; and instructions for generating hardware codes of power elements included in the power management controller, register codes corresponding to the respective power elements, hardware codes corresponding to the plurality of ports and connections, and binary codes corresponding to a working sequence of the power management controller.

The present invention provides a display device and an electrical terminal including a display panel, a driver electrically connected to driving a display panel to display images, a power manager electrically connected to the driver. A first voltage module (included in the power manager) includes a first transistor and a second transistor. The power manager is configured to at least one of the first transistor and the second transistor to switch on according to a value of a first current of the first voltage module transmitted to the driver control. Also, three conversion efficiencies of the first voltage module respectively in conditions of only the first transistor switching on, only the second transistor switching on, and both the first and second transistors switching on are different to reduce power consumption of the display device.

Systems, apparatuses, and methods for a host controller inferring idleness based on activity generated by a bus-attached peripheral device are disclosed. A host controller detects activity by a first device attached to the host controller via a first bus. The host controller generates an activity vector based on the detected activity, and the host controller determines whether the activity vector indicates that the first device is only engaging in handshaking or control activity rather than data transfer. If the first device is merely communicating status information, then the host controller infers idleness and conveys an idleness indicator to a power manager. The power manager turns off power to system memory and / or other components based on the idleness indicator, but keeps enough power on to allow the host controller to communicate with the first device for handshaking or status purposes.

The technology is generally directed to multi-channel memory in a system on chip (SoC) device. Multiple memory channels are associated with a single common microcontroller instead of including a microcontroller with each channel. The common microcontroller is located centrally on the chip along with the memory subsystem. The single microcontroller receives commands from a plurality of host processing entities (PEs) including one or more of a central processing unit, a debugging architecture, and a power manager The processor receives commands from the host PEs from a software sequencer of the compute device, while the single microcontroller communicates with each of the plurality of memory channels through an advanced peripheral bus. The single microcontroller aggregates requests from the host PEs and manages the programming of the memory controller, the PHY, and the dynamic random access memory for the plurality of memory channels.

The present invention provides a display device and an electrical terminal including a display panel, a driver electrically connected to driving a display panel to display images, a power manager electrically connected to the driver. A first voltage module (included in the power manager) includes a first transistor and a second transistor. The power manager is configured to at least one of the first transistor and the second transistor to switch on according to a value of a first current of the first voltage module transmitted to the driver control. Also, three conversion efficiencies of the first voltage module respectively in conditions of only the first transistor switching on, only the second transistor switching on, and both the first and second transistors switching on are different to reduce power consumption of the display device.

1. The name of the design product: Internet of Things power manager. 2. The use of the design product: support local area network or wide area network and platform connection function. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

Power supply system for electrical equipment, characterized in that it comprises the following: an energy manager with an input end connected to a power generation module and an output end connected to a DC bus; at least one inverter assembly, the inverter assembly comprising a rectifier module and an inverter module; the rectifier module having an input end connected to a supply network to rectify AC load power into a DC voltage and output the DC voltage to the DC bus; the inverter module having an input end connected to the DC bus and an output end that outputs AC power to supply power to a load device; wherein the energy manager is configured with an energy management strategy which includes: regulating power coming in from the supply network according to the power generated by the power generation module in order to maintain a DC bus voltage within a preset range to supply power to the consumer device.

The embodiment of the present application provides a kind of server and method, for promoting the utilization efficiency of computer room power resource.The embodiment of the present application includes: first PDU, second PDU and battery and power manager;Battery, with first PDU and second PDU electric connection, for when first power fails, by a PDU, for power unit provides the electric energy of first power, when second power fails, by second PDU, for power unit provides the electric energy of second power;Power manager, with first power, second power and battery electric connection, when first power fails, first power signal is sent to battery, indicates for power unit provides the electric energy of first power;When second power fails, second power signal is sent to battery, indicates for power unit provides the electric energy of second power.By the cooperation of battery and power manager, without long-term one-way power supply as backup, eliminate the resource waste caused by one-way power supply as backup, promote the utilization efficiency of computer room power resource.

An audio / video (A / V) recording and communication doorbell includes a camera, a speaker, a microphone, a power manager, a battery, an AC / DC rectifier, and a DC / DC converter. The doorbell is configured to be connected to an external AC power source through the AC / DC rectifier and the DC / DC converter. The power manager is configured to draw power from the AC power source up to a threshold power and to draw supplemental power from the battery such that the power drawn from the AC power source never exceeds the threshold power. Thus, the A / V recording and communication doorbell herein can be connected to an existing household AC power source and an existing doorbell signaling device without causing inadvertent sounding of the signaling device.

The application provides a voltage reduction converter and power manager, wherein the voltage reduction converter comprises: a phase-locked loop circuit for generating a frequency modulation current signal and a synchronous clock signal according to a received external clock signal and a frequency adjustment value output by the frequency modulation element; and at least one channel circuit for outputting a voltage input by an external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency modulation current signal. The application comprises the phase-locked loop circuit and the channel circuit, and the channel circuit outputs the voltage input by the external power supply at the corresponding output frequency according to the frequency modulation current signal and the synchronous clock signal generated by the phase-locked loop circuit, so that the working frequency of the voltage reduction converter is not limited to one frequency, but can be adjusted in a wide range. At a certain working frequency, the working frequency is not affected by working conditions such as input voltage and output voltage.

Some logic circuits in an IC may have periods of inactivity, such as when the functions they provide are not needed, but they continue to consume power. In an exemplary IC, a power manager determines that a logic circuit is in an inactive state, employs a lookup table circuit to determine an optimal low-power mode (LPM) for the logic circuit based on an anticipated duration of the inactive state, and causes the circuit to enter the optimal LPM. Determining an optimal LPM from a lookup table circuit minimizes the latency of the LPM determination. Determining an optimal LPM may include comparing net energy consumptions of LPMs with different rates of power consumption. In some examples, the power manager provides at least one of a circuit identifier, a circuit frequency, and a memory interface frequency to the lookup table circuit and receives the optimal LPM.