12 results about "Test complexity" patented technology

This invention relates to the field of aircraft strength testing technology, and discloses a load reduction device and method for aircraft wing top-mounted strength testing. It utilizes the lever principle to apply a downward load reduction load to the wing to balance the upward top-mounted load borne by the wing top point, thus reducing the overall load on the aircraft to zero and achieving the purpose of load reduction. This invention uses the lever principle to reduce the output load of the hydraulic actuator, achieving small load balancing of extremely large loads. Furthermore, for extremely large single-point loads at a single top point, only a few load reduction load application points need to be applied, reducing the loading channels for the load reduction load and lowering the test complexity. By using the small load of the hydraulic actuator to balance the extremely large load at the top point, the safety and reliability of the test are improved, solving the reliability and safety problems of balancing extremely large single-point loads in wing top-mounted strength testing.

The invention relates to an FPGA (Field Programmable Gate Array)-based ADC (Analog to Digital Converter) verification device and a verification method thereof. The FPGA-based ADC verification device comprises an ADC board card interface module, a clock module, an FPGA module and a power module, the output end of the ADC board card interface module is connected with the FPGA module; the output end of the clock module is connected with the FPGA module; and the output end of the power supply module is connected with the FPGA module. According to the method, the batch full-automatic test of the verification parameters of the ADC sampling board card is realized, and the final channel verification parameter value is calculated and sent to the upper computer, so that the test complexity is simplified, the test efficiency is greatly improved, and the labor cost is reduced.

This invention provides a hub device. The hub device includes: a base, a first connecting assembly having a first through hole, a rotating member having a second through hole, and a second connecting assembly; the rotating member is disposed in the first through hole of the first connecting assembly, and the second connecting assembly is disposed in the second through hole of the rotating member; the rotating member is rotatable on the base; the first connecting assembly includes multiple access ports, each access port for connecting a device under test (DUT); the second connecting assembly is used for connecting to an external device; the sidewall of the rotating member has a conductive structure; when the rotating member is rotated until the conductive structure aligns with a target access port among the multiple access ports, the conductive structure connects the target DUT connected to the target access port and the external device. This invention, by operating the rotating member to rotate, can control the connection of an external device to different DUTs, allowing the DUTs to be quickly switched in a short time, thereby reducing testing complexity and improving testing efficiency.

The invention relates to the technical field of high-speed interface verification and system-level prototype verification, in particular to an FPGA prototype verification platform based on an MIPI loop, which comprises an upper computer PC, an FPGA main control chip, a PCIe interface module, a Decoder module, an MIPI sending module, an MIPI physical interface module, an MIPI receiving module and a verification module. The MIPI sending module and the MIPI receiving module are in direct loop connection through a dual-channel FPC flat cable. The verification module is a configurable verification area and is used for deploying a to-be-tested MIPI protocol module on the FPGA to realize function and performance verification of the to-be-tested MIPI protocol module in a closed-loop environment; the verification module can load different circuit modules, and performs on-line verification on data sending, receiving and time sequence logic of the different circuit modules; verification data is sent through the upper computer, enters the FPGA through the high-speed PCIe interface, and enters the MIPI sending module through the decoding module. According to the platform, functional verification and performance evaluation of any module based on the MIPI protocol can be completed under the condition of not depending on external real equipment, and the test complexity and cost are greatly reduced.

The invention relates to the technical field of aircraft strength tests, and discloses an aircraft wing jacking strength test load shedding device and method, which utilize the lever principle to apply a downward load shedding load to a wing so as to balance an upward jacking load borne by a wing jacking point, so that the load borne by the whole aircraft is zero, and the purpose of load shedding is achieved. According to the invention, the output load of the hydraulic actuator cylinder is reduced by using the lever principle, the balancing of a small load and an ultra-large load is realized, and for an ultra-large single-point load of a single top starting point, the load shedding load only needs to be applied to fewer load shedding load acting points, so that the loading channels of the load shedding load are reduced, the test complexity is reduced, and the test efficiency is improved. The small load of the hydraulic actuator cylinder is used for balancing the ultra-large load of the top starting point, so that the safety and reliability of the test are improved, and the problems of reliability and safety of ultra-large single-point load balancing in the wing jacking strength test are solved.

The embodiment of the present application relates to a kind of based on module image recognition's communication module switching method and equipment, the method includes: continuously listening to control instruction;When instruction code is switching instruction code, test circuit type, test-switching relationship table and test-module relationship summary table are extracted;Call camera to generate corresponding first image by shooting the overhead view of spring needle array that communication module is pressed into;And image recognition is carried out to first image to obtain panoramic segmentation graph;According to panoramic segmentation graph, test circuit type and test-module relationship summary table, the connection of communication module and spring needle array is confirmed and the connection of test circuit and communication module is confirmed;According to test-switching relationship table, module-switching relationship table and test-module relationship table, switching switch of switching module is switch on or off or disconnecting operation.It can reduce test complexity, improve test efficiency, save test cost by the present application.

This invention relates to the field of aircraft structural design technology, specifically disclosing an aileron testing device and method for simulating wing deformation. The aileron testing device includes a base, multiple connectors, and multiple drive components. Utilizing this aileron testing device, the drive components move the connectors, which in turn move the aileron joint under test. This simple control process effectively shortens the overall aircraft testing cycle for ailerons. While achieving ground-based bench testing of aileron deformation, it reduces the workload of aileron loading and measurement, simplifies testing complexity, saves testing costs, and shortens the overall aircraft testing cycle.

The invention provides a test method and a test system for a printed circuit board. The test system comprises an upper computer and an accompanying test board, and the method comprises the following steps: responding to a signal triggered by a test fixture when the printed circuit board is placed on the test fixture, and sending a test starting signal to the upper computer by the accompanying test board; in response to the test starting signal, the upper computer generates a test control instruction according to preset configuration information and sends the test control instruction to the test accompanying board; the test accompanying board performs test operation on the printed circuit board according to the test control instruction, obtains test data of the printed circuit board and sends the test data to the upper computer, and the test data comprises external measurement data and internal operation data of the printed circuit board; and the upper computer determines the rationality of the test data according to a judgment rule defined by the configuration information, and obtains a test result of the printed circuit board. By using the method, the test complexity can be reduced, the debugging time can be shortened, and the test efficiency can be improved.

The invention relates to the technical field of storage testing, and discloses a DDR testing method, device and equipment and a computer readable storage medium. The method comprises the following steps: acquiring a bus signal of a test DDR, determining a first read address based on the bus signal, and reading first data from the test DDR based on the first read address; performing address mapping on the first read address on the basis of a preset unified logic address space and the type of a preset standard DDR to obtain a second read address, and reading second data from the preset standard DDR on the basis of the second read address; and comparing the first data with the second data to determine a test result for testing the DDR. The read data of the test DDR have the read data of the corresponding preset standard DDR, accidental errors occurring in a real scene are covered, meanwhile, only the read data of the test DDR and the read data of the standard DDR need to be compared, the accuracy of the DDR test is improved, and the complexity of the DDR test is reduced.

The invention provides a data testing method and device, equipment, a storage medium and a program product, and relates to the technical field of communication. The method comprises the following steps: executing preset three-layer attribute mapping according to an attribute initial value input by a user, and determining an input parameter initial value of a three-layer application programming interface; judging the message type according to the return parameter of the three-layer application programming interface; and corresponding response messages are generated for different message types according to a preset mode, and data testing is completed. According to the method and the device, the initial data is converted into the input parameter initial value of the three-layer application programming interface through the preset three-layer attribute mapping, so that the problem of high data test complexity caused by the fact that the three-layer application programming interface is developed by different platforms is solved.