The application discloses a
chip and a
chip debugging
system, and relates to the technical field of
chip debugging. The chip comprises a controller, a reset
signal generating unit, an instruction receiving unit, an interface
multiplexing unit, a debugging module, a
functional module and a general interface. The general interface is used for connecting with a
debugger, and the instruction receiving unit is connected with the general interface. The reset
signal generating unit is used for generating an effective first reset
signal and a second reset signal. The
release time of the first reset signal is earlier than the
release time of the second reset signal. The instruction receiving unit is used for detecting whether an instruction sent by the
debugger is received after the release of the first reset signal and before the release of the second reset signal. When the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface
multiplexing unit to select the general interface and the debugging module. When the instruction receiving unit does not receive the instruction, the controller controls the interface
multiplexing unit to select the general interface and the
functional module. According to the application, no additional multiplexing control pin is needed, and flexible multiplexing of a debugging interface and a
functional interface is realized.