1090 results about "Interface (computing)" patented technology

A system has a virtual overlay infrastructure mapped onto physical resources for processing, storage and network communications, the virtual infrastructure having virtual entities for processing, storage and network communications. Virtual infrastructures of different users share physical resources but are isolated and have their own management entities. An interface between infrastructures allows controlled relaxation of the isolation, using a gateway between virtual nets, or shared virtual storage devices. This can allow businesses to share data or applications, while maintaining control of security.

A robotics process automation platform for developing and managing a workflow is provided. The platform includes development and operational databases stored in a memory, a development interface component, a control interface component, and a runner component. The development interface component is configured for creating a workflow and storing the workflow in the development database. The control interface component is configured for selecting the workflow stored in the development database and storing a copy of the workflow in the operational database. The runner component is configured for receiving instructions from the control interface component to store a copy of the workflow stored in the operational database in a memory of a virtual computing device, and downloading the workflow in the second memory. The runner component is also configured for instructing the virtual computing device to execute the workflow in association with the target application.

The Field Programmable Instrument Controller (FPIC) is a stand-alone low to high performance, clocked or unclocked multi-processor that operates as a microcontroller with versatile interface and operating options. The FPIC can also be used as a concurrent processor for a microcontroller or other processor. A tightly coupled Multiple Chip Module design incorporates non-volatile memories, a large field programmable gate array (FPGA), field programmable high precision analog to digital converters, field programmable digital to analog signal generators, and multiple ports of external mass data storage and control processors. The FPIC has an inherently open architecture with in-situ reprogrammability and state preservation capability for discontinuous operations. It is designed to operate in multiple roles, including but not limited to, a high speed parallel digital signal processing; co-processor for precision control feedback during analog or hybrid computing; high speed monitoring for condition based maintenance; and distributed real time process control. The FPIC is characterized by low power with small size and weight.

A partitioned processing system is disclosed wherein applications in a plurality of partitions can share an I/O operation program (or device driver). In one embodiment, memory is shared between the partitions to provide a communication path (interface) to the driver. In one embodiment, a computing system has a first partition including a first operating system and a first block of system memory. The computing system further has a second partition including a second operating system and a second block of system memory. An application in the first partition initiates an I/O request using an interface, and an I/O operation program in the second partition receives the I/O request. The I/O device driver then uses the interface to communicate the results of said I/O request with the application.

An access server computing system scrapes a set of records maintained by a target computing system in a database which is only made accessible over the Internet with a limited protocol query and an access challenge. The access server accesses the target computing system through an Internet browser interface based on emulating a user query made through the limited protocol, including by automatically passing locator identifier fields to retrieve a corresponding set of record which are stored in the first database.

A remote high-performance computing material joining and material forming modeling system (100) enables a remote user (10) using a user input device (20) to use high speed computing capabilities to model materials joining and material forming processes. The modeling system (100) includes an interface module (200), an application module (300), a computing module (400), and a scheduling module (500). The interface module (200) is in operative communication with the user input device (20), as well as the application module (300), the computing module (400), and the scheduling module (500). The application module (300) is in operative communication with the interface module (200) and the computing module (400). The scheduling module (500) is in operative communication with the interface module (200) and the computing module (400). Lastly, the computing module (400) is in operative communication with the interface module (200), the application module (300), and the scheduling module (500).

A method of automated deployment managed by a service provider, of a computer based business process, involves generating a model (730) of the business process including a design of computing infrastructure, and deploying the model on hardware (770) dedicated to the enterprise, with an interface for the service provider to enable ongoing management of the deployed process by the service provider. Having dedicated hardware means the location of the hardware can be arranged to suit the enterprise. This means limitations such as bandwidth or latency of WAN links, can be addressed by choosing the location of the dedicated hardware appropriately. Trust of security can also be increased compared to that of the shared data centres. The automated model driven deployment can help enable the service provider to provide such deployments on different types of hardware. The need for the enterprise to maintain specialist expertise in house is reduced.

The invention provides a central office metaphor to computing, where features and functions are provided by a one or more servers and communicated to an appliance terminal through a network. Data providers are defined as “services” and are provided by one or more processing resources. The services communicate to display terminals through a network, such as Ethernet. The terminals are configured to display data, and to send keyboard, cursor, audio, and video data through the network to the processing server. Functionality is partitioned so that databases, server and graphical user interface functions are provided by the services, and human interface functionality is provided by the terminal. Communication with the terminals from various services is accomplished by converting disparate output to a common protocol. Appropriate drivers are provided for each service to allow protocol conversion. Multiple terminals are coupled to the network. Users can enable their unique session at any one of the terminals by inserting a “smart card” into a card reader. Removing the card disables the session. Re-inserting the card into the same or any other terminal re-enables the session.

Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision, the input data, preferably a qubit, is collapsed to a point value within the quantum gap based on a software instruction. After collapse the input data is restructured at the destination, wherein dynamics of restructuring are governed by a plurality of gap factors as follows: computational self-awareness; computational decision logic; computational processing logic; computational and network protocol and logic exchange; computational and network components, logic and processes; provides the basis for excitability of the Gap junction and its ability to transmit electronic and optical impulses, integrates them properly, and depends on feedback loop logic; computational and network component and system interoperability; and embodiment substrate and network computational physical topology.

Aspects of the present invention relate to a multi-sided hand-held controller for a head-worn computing system. The hand-held computer controller includes a first user control interface on a first side of the hand-held controller, a second user control interface on a second side of the hand-held controller, and a control system adapted to detect which of the first side and second side is an active control side of the controller, positioned properly for user interaction. Following the detection, the control system can activate the active control side to accept user interactions for control of a computer.

The invention discloses a dynamic measuring method based on dependable computing and a management system. The management system interacts with a user through a user management interface of an operation system and application programs. The management system comprises a dynamic measurement control module interacting with the operation system, wherein the dynamic measurement control module controls a judgment module, an audit module and a measuring module, the judgment module obtains a latest measurement result from the audit module and judges whether the operation system is dependable or not according to a strategy, the measuring module is responsible for detecting the dependable state of the operation system in operation, the audit module is responsible for calculating, storing and reporting measurement results in a classified mode, the control module is responsible for configuring external management programs to other modules, sending system state information to the external management programs and providing access ports of trusted software special hardware for the modules. The management system works in a kernel layer, the system can guarantee integrity of the modules once starting static measurement, and credibility and safety are improved.

The invention provides a matrix processor as well as an instruction set and an embedded system thereof. The matrix processor comprises an external data interface, an IRAM (intelligent random access memory), a DRAM (dynamic random access memory) and a matrix processor core, wherein the external data interface is connected with the IRAM and the DRAM of the matrix processor as well as an external memory so as to write an instruction of the matrix processor and perform data exchange with the outside; the IRAM and the DRAM are equivalent to buffers of the matrix processor; the IRAM receives an instruction sequence written by an external module; the DRAM receives a matrix or other data written by the external module as well as computing results written by the matrix processor core so that the matrix or data and the computing results are used by the matrix processor or are read by the external module so as to complete data exchange between the matrix processor and the external module; and the matrix processor core is used for fetching the instruction, decoding, computing, and writing back and controlling the computing results. The matrix processor provided by the invention can independently complete various matrix operations and other mathematical operations.

A method for static code analyzing customizations to a pre-packaged computing solution can include establishing a communicative connection from a recommendation generation module to a pre-packaged computing solution and authenticating into the pre-packaged computing solution. Customized program code can be extracted from the pre-packaged computing solution and a call graph of the customized program code can be constructed such that the call graph indicates method calls to different interfaces for program code of the pre-packaged computing solution. Finally, a report can be generated identifying customized program code to be adapted to a new version of the pre-packaged computing solution based upon changes in the different interfaces shown by the call graph to be used in the new version of the pre-packaged computing solution and modifications required for the customized program code to call the different interfaces in the new version of the pre-packaged computing solution.

A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Aspects of the present disclosure relate to systems and methods for virtualizing mass storage using an interface card, or other special hardware unit, operatively coupled to a host system. In various implementations, the interface device and host system may collectively emulate a mass storage device for another “terminal” computing system in a manner that is transparent to the terminal system. Moreover, in various implementations, a mass storage device may be emulated in a manner that is transparent to the terminal system, without requiring modifications to the terminal platform's hardware or software architecture.

The invention sets forth an approach for aggregating a plurality of NICs in a computing device into a single logical NIC as seen by that computing device's operating system. The combination of the single logical NIC and a network resource manager provides a reliable and persistent interface to the operating system and to the network hardware, thereby improving the reliability and ease-of-configuration of the computing device. The invention also may improve communications security by supporting the 802.1X and the 802.1Q networking standards.

A computing system in which a human interface (HI) is located remotely from a computer. The HI includes a keyboard, mouse, and monitor. The computer includes a motherboard with CPU, memory, network and interface logic, disk drives, and a power supply, configured on a single card, and communicates with the HI by sending and receiving encoded HI signals. The computer card includes an interfacing edge connector for communicating with the HI and networks. The HI logic receives HI signals from the interface logic and encodes the signals into a format suitable for transmission to the HI. The HI logic receives and decodes incoming encoded HI signals from the HI, and transmits the decoded HI signals to the interface logic for use in the computing system. The network logic encodes network signals into a format suitable for transmission to the network, and receives and decodes encoded network signals from the network.