29 results about "Power Architecture" patented technology

The invention discloses a whole vehicle power hardware-in-the-loop simulation test system and method under a P2.5 + P4 hybrid architecture. The whole vehicle power hardware-in-the-loop simulation test system comprises a controller, a test cabinet and an upper computer system, the hybrid power gearbox control system is electrically connected with the high-voltage control system; the test cabinet is electrically connected with the hybrid power gearbox control system, the high-voltage control system and the upper computer system; the upper computer system comprises a management module, a signal interface module, a controller interface module and a virtual simulation vehicle module, the management module is connected with the test cabinet and the signal interface module, and the signal interface module is used for realizing signal interaction between the controller interface module and the management module; the controller interface module is connected with the signal interface module, the Soft ECU module and the power simulation module. Standardized development of the power simulation test system is realized, the modular design supports rapid adaptation of different vehicle type platforms and power architectures, and repeated development is reduced.

The invention discloses an embedded AI intelligent computing power architecture method, and particularly relates to the technical field of artificial intelligence processing architecture. Collecting a resource state parameter set R of the embedded device; obtaining a to-be-executed AI task set T, wherein each task comprises model complexity, real-time requirements, expected response duration and priority; constructing a computing power resource allocation evaluation function F based on R and T, and outputting a task scheduling priority score; allocating tasks to the embedded AI module according to the allocation scheme and executing reasoning; the resource state is dynamically monitored in the task running process, and if it is predicted that resources are about to be overloaded, a scheduling function F is triggered to reconstruct a resource allocation scheme; performing iterative optimization on weight parameters in the function F based on task history feedback; by means of the method and device, optimal adaptation of multi-task concurrent scheduling can be achieved under the condition that resources are limited, the computing power resource utilization rate, the response efficiency and the system stability are improved, and the method and device are suitable for various edge side AI scenes.

This invention provides a method and system for predicting vehicle speed in commercial vehicles using the E-Power architecture, relating to the field of commercial vehicle speed measurement technology. First, vehicle operating data is collected via hardwired and CAN bus lines. Second, the PCA method is used to extract features from the collected vehicle operating data, obtaining variables highly correlated with vehicle speed, which serve as input to the speed prediction model, improving computational efficiency. Finally, a speed prediction model is established based on a recursive fuzzy neural network and a multi-step prediction strategy, achieving accurate prediction of vehicle speed during operation and improving fuel economy and driving comfort.

Systems and methods are described for applying one or more frequency domain analyses to AC components to automatically discriminate between different operating conditions of the power architecture. Embodiments can then adaptively adjust the voltage (e.g., and current) to reduce or eliminate extra power consumption based on the detected operating condition. In some embodiments, the frequency domain analyses are based on fast Fourier transform (FFT) techniques and / or total harmonic distortion (THD) techniques. Embodiments can be applied to internal power modules and / or to external power adapters.

The application relates to the technical field of cloud computing resource allocation, and discloses a heterogeneous computing power cooperative allocation method and system, which comprises the following steps: S1, characteristic modeling is performed on all-network heterogeneous computing power nodes in advance, a heterogeneous computing power characteristic matrix M containing computing power architecture types, available computing power scales, current load rates, available bandwidths, local storage reserves and real-time power consumptions is constructed, wherein the heterogeneous computing power nodes include four types of heterogeneous resource nodes, namely, general-purpose CPUs, general-purpose GPUs, AI acceleration NPUs and edge computing nodes; the application constructs a multi-dimensional quantitative heterogeneous adaptation model, three quantitative calculation formulas are introduced to respectively realize the calculation of an adaptation score, a total allocation cost and a dynamic correction coefficient, multiple optimization targets, such as architecture adaptability, power consumption, time delay, migration overhead and computing power fragmentation, are included in the allocation model, the accurate matching of the heterogeneous computing power nodes and to-be-allocated tasks can be realized, the performance advantages of different architecture heterogeneous computing powers can be fully exerted, and the overall computing power resource utilization rate can be effectively improved.

According to at least one aspect of the disclosure, a uninterruptible power supply includes a first input configured to be coupled to, and receive main power from, a main power source, a second input configured to be coupled to, and receive backup power from, a backup power source, an output configured to be coupled to at least one load, at least one current sensor, a four-quadrant inverter coupled to the first input, the second input, and the output, and at least one controller configured to control the four-quadrant inverter to provide power derived from the first input to the second input to charge the backup power source, and provide power derived from the second input to the output to supplement the main power.

A method for managing power resource in an augmented reality (AR) device is described. In one aspect, the method includes configuring a low-power mode to run on a low-power processor of the AR device using a first set of sensor data, and a high-power mode to run on a high-power processor of the AR device using a second set of sensor data, operating, using the low-power processor, a low-power application in the low-power mode based on the first set of sensor data, detecting a request to operate a high-power application at the AR device, in response to detecting the request, activating the second set of sensors of the AR device corresponding to the high-power mode, and operating, using the high-power processor, a high-power application in the high-power mode based on the second set of sensors.

The invention discloses a DSC decoder low-power-consumption architecture implementation method applying a power consumption dynamic isolation technology. A code stream pre-analysis unit, a BP vector pre-search unit, a P mode power consumption control unit used for dynamically isolating P mode power consumption and an ICH behavior simulation unit used for dynamically isolating I mode power consumption are included. The power consumption in the DSC decoding process mainly comes from prediction reconstruction in a P mode and coding index updating in an I mode, so that the power consumption of the P mode and the power consumption of the I mode of a decoder are dynamically isolated to achieve accurate power consumption control optimization. And the power consumption of the DSC decoder is obviously reduced.

Smart Dual-Patient Acupuncture Machine with Regulated Power Architecture

The invention discloses a modular digital variable inductance device based on coarse and fine coordinated modulation and a control method thereof, and belongs to the technical field of power electronic magnetic elements. The invention provides a digital variable inductor module integrating a hybrid magnetic circuit topology and an embedded control unit in order to solve the problems that the adjustment range and the adjustment precision of a traditional variable inductor are difficult to consider at the same time and direct interaction with a digital control system is difficult. According to the module, the topology that a multi-magnetic-core-section discrete inductance adjustment unit (coarse adjustment) and a magnetic control continuous inductance adjustment unit (fine adjustment) are connected in series is adopted on a power framework, and an externally input digital or analog inductance demand instruction is analyzed into a hierarchical control signal through a built-in microcontroller on a control framework. Stepless, smooth and high-precision adjustment of an inductance value in a wide range is realized through large-span step switching of the coarse adjustment unit and linear interpolation compensation of the fine adjustment unit.

The invention discloses a multi-layer intermediate representation compiler implementation method based on RISC-V open source chip hardware perception, and belongs to the technical field of computer systems and compilation. The method comprises the steps that hardware feature data are acquired, and a hardware feature database is formed; a hierarchical controllable IR exposure mechanism is adopted, and according to hierarchical intermediate representation and a hardware feature database, an intra function related source code for specific hardware feature data is generated based on a three-level general computing power architecture of an RISC-V open source chip instruction set and an extended instruction set; and compiling the scalar-related source code and the intra-function-related source code in the user source code into an executable file or a binary library by using a general compiler, or compiling the intra-function-related source code into the executable file or the binary library by using the general compiler. The multi-layer intermediate representation compiler implementation method based on RISC-V open source chip hardware perception can quickly adapt to a novel chip and closely fit hardware, and efficient, super-heterogeneous and super-parallel code generation is achieved.

To improve energy efficiency and safety during the operation of an elevator system (1), an electrical power architecture is proposed which includes as its central component a regenerative elevator frequency converter (2) configured to supply motor currents for an elevator motor (8) of the elevator system (1). This frequency converter (2) has an input-side AFE converter (5) capable of feeding energy back from a DC intermediate circuit (3) of the frequency converter (2), mediated via the AFE converter (5), into a building power grid (13) and / or into an input-side connected AC supply network (7), particularly in response to corresponding control signals or consumption information that the frequency converter (2) obtains from a smart meter (14) via a corresponding communication link (17).Furthermore, the architecture preferably also provides a regenerative energy source (11) which is electrically connected directly to the DC intermediate circuit (3) of the frequency converter (2) via a unidirectional electrical converter (12).

A gate ground (GTD) cell utilizing a backside power delivery scheme is disclosed in which metal lines that deliver power are disposed on the backside of a wafer. Thus, an ultra-low height standard cell may be implemented. And relatively high area miniaturization can be realized. In addition, performance and power gain may be maximized.

This application discloses a method, system, apparatus, and storage medium for generating a power tree. The method includes: acquiring power architecture information input by a user, the power architecture information including each load point and its corresponding load point parameters; sorting each load point according to a preset sorting rule to obtain a sorting result; matching each load point with a corresponding power type according to the sorting result and a preset power type determination rule to obtain several power nodes; constructing an initial power tree based on the hierarchical relationship of the power nodes; and selecting matching power devices from a device database according to device matching rules based on the voltage and current parameters of each power node in the initial power tree, and constructing a final power tree based on the power devices. This application reduces the reliance on personal experience through matching rules, thereby reducing design defects caused by experience differences and automating the process from parameter input to power tree generation.

The invention discloses a power supply virtualization management system based on a microkernel mechanism, and relates to the technical field of interface management, a Hypervisor power supply virtualization architecture and a mail-box mechanism reduce faults, are of great significance to key businesses of an enterprise data center, can avoid interruption of businesses such as financial transactions and an ERP system, and a CPU frequency modulation and Thermal regulation and control module ensures system stability under different working conditions, so that the power supply virtualization management system has a good application prospect. A mail-box mechanism reduces the hardware updating risk and ensures that services are not stopped, a Hypervisor power supply architecture optimizes power supply management, the efficiency is improved through interaction of a User OS and a ServiceOS, the energy cost is reduced, the server performance is ensured, the service process is accelerated, and the office efficiency is improved. CPU frequency modulation and a Thermal regulation strategy balance performance and power consumption to meet requirements of different departments, a mail-box mechanism ensures security isolation, prevents information leakage in a multi-system environment, protects core data, ensures security of sensitive data such as data center finance and the like, a CPU hot plug mechanism prevents hardware and data problems, the mail-box mechanism ensures instruction transmission and execution in an industrial automation scene, and the safety of the industrial automation scene is ensured. And the production efficiency and quality are improved.

Apparatus and associated methods relate to a modular energy conversion system (MECS). In an illustrative example, the MECS may include a distributed power converter having a first and second subsets of hybrid converter modules (HCMs). For example, output ports of the first subset of HCMs may be electrically connected in series to form an upper arm, and the output ports of the second subset of HCMs may be electrically connected in series to form a lower arm. The upper and lower arms may be electrically connected at a first end to form a connection point. A unipolar voltage source may be electrically connected to an opposite end of the connection point of the upper and lower arms. A power combiner unit (ECU) may be physically separated from and electrically connected to the connection point. For example, the PCU may be configured to measure electrical property at the connection point and adaptively regulate AC power generated at the connection point based on the measured electrical property. Various embodiments may advantageously enable efficient integration of distributed renewable energy sources and energy storage while providing power scaling through a modular architecture.

The invention discloses an integrated power supply framework, a power supply system and a vehicle, which are characterized in that an accessed first voltage is converted into a second voltage through a first voltage conversion circuit to charge a power battery pack, or the second voltage provided by the power battery pack is converted into the first voltage to be output; the second voltage conversion circuit converts a second voltage provided by the first voltage conversion circuit or the power battery pack into a third voltage, and the power supply distribution circuit receives the third voltage and distributes electric energy to a plurality of load power supply ends; the first voltage conversion circuit, the second voltage conversion circuit and the power supply distribution circuit share the same controller, so that the functions of vehicle-mounted charging and discharging and low-voltage distribution are integrated in vehicle power supply, the integration level of the system is improved, the response time of each functional circuit is reduced, the use of wire harnesses, connectors and the like is reduced, and the cost is reduced.

The invention discloses a capacitive gate real-time measurement system based on a dual-power architecture, and relates to the technical field of capacitive gate measurement systems, and the system comprises a power input module, a power conversion module, a main power supply path and an auxiliary power supply path. The power conversion module is connected with the power input module, the main power supply access and the auxiliary power supply access. The power input module is used for providing external electric energy input; the power conversion module is used for controlling on-off of the main power supply path and the auxiliary power supply path; the auxiliary power supply access is used for acquiring a measurement result; the main power supply path is used for processing the measurement result and controlling the power conversion module. According to the invention, ultra-low power consumption operation of the capacitive gate measurement module is realized by setting the power supply conversion module, and seamless connection and instantaneous wakeup of absolute position data in any on-off state are supported.

A method for managing power resource in an augmented reality (AR) device is described. In one aspect, the method includes configuring a low-power mode to run on a low-power processor of the AR device using a first set of sensor data, and a high-power mode to run on a high-power processor of the AR device using a second set of sensor data, operating, using the low-power processor, a low-power application in the low-power mode based on the first set of sensor data, detecting a request to operate a high-power application at the AR device, in response to detecting the request, activating the second set of sensors of the AR device corresponding to the high-power mode, and operating, using the high-power processor, a high-power application in the high-power mode based on the second set of sensors.

The invention discloses a novel electric power architecture system and a control method thereof, the system comprises a current source for providing an output current Io, a voltage stabilizer, an electric energy buffer device and a control unit, when the output current Io of the current source is smaller than a required current IL of a load, the electric energy buffer device is controlled to be in a discharge state so as to supplement electric energy to the load, the release current Ib1 of the electric energy buffer device is equal to IL-Io, when the output current Io of the current source is larger than the required current IL of the load, the electric energy buffer device is controlled to be in a charging state so as to absorb redundant electric energy output by the current source, and the charging current Ib2 of the electric energy buffer device is equal to Io-IL. According to the invention, the electric energy buffer device is allowed to respond to the rapid fluctuation of the load power at the microsecond level, the electric energy buffer device can completely provide the current required by the load when the current source works abnormally, and the damage to the power grid end caused by the rapid fluctuation of the power of the data center and the redundancy requirement on the power architecture are fundamentally solved.

The invention discloses an STE high-speed decoding device and system for realizing autonomous and controllable domestic computing power, and solves the problems of monopoly, low decoding efficiency and poor safety controllability of an overseas computing power architecture. According to the invention, domestic hardware is used as a base, an STE high-speed decoding core unit is integrated, and based on STE coding rules and proportional philosophy, parallel layered decoding, dynamic computing power scheduling and national security level security verification are adopted, so that a decoding rate greater than or equal to 10 bit / s is realized. A special hardware instruction set is expanded at a chip end, and the ST-ALU and the cache are integrated, so that the decoding delay is greatly reduced; and the AI large model end realizes inference decoding lossless restoration and full-link credible verification, and eliminates distortion and security risks. The method is autonomous, controllable, high in speed, low in time delay, high in safety and suitable for national computing power infrastructure, AI large model deployment and high-performance computing, and the domestic computing power competitiveness and the safety guarantee capability can be remarkably improved.

A method for communicating test information, includes providing a data stream to a circuit block that is implemented on a semiconductor die, demultiplexing data channels from the data stream, multiplexing the data channels to obtain a modified data stream after test information collected from a plurality of sections of the circuit block has been inserted into one or more data channels allocated to at least one section of the circuit block by corresponding embedded distributed test (EDT) circuits implemented in the at least one section of the circuit block, and transmitting the modified data stream to another circuit block implemented on the semiconductor die.

The present invention discloses a method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception, belonging to the field of computer systems and compilation technology. The method comprises the following steps: obtaining hardware feature data to form a hardware feature database; adopting a hierarchical and controllable IR exposure mechanism, and generating intrinsic function-related source code for specific hardware feature data based on the hierarchical intermediate representation and the hardware feature database, based on a three-level general computing power architecture of the RISC-V open source chip instruction set and extended instruction set; using a general compiler to compile scalar-related source code and intrinsic function-related source code in user source code into an executable file or binary library, or using a general compiler to compile intrinsic function-related source code into an executable file or binary library. The method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception can quickly adapt to new chips and closely match the hardware, achieving efficient super-heterogeneous and super-parallel code generation.

The invention discloses a lightweight intelligent module carried on an unmanned aerial vehicle, and the module comprises a calculation module, an acquisition module, a communication module, a storage module and an interface module. The calculation module employs a high-efficiency low-power-consumption architecture, integrates a special AI acceleration chip, and internally integrates a special central processing unit CPU and a neural network processing unit NPU. Neural network reasoning optimization is realized through a heterogeneous computing architecture; the acquisition module is provided with a multi-channel data acquisition interface and is internally provided with a data preprocessing unit, and a framework is processed in a multi-thread parallel mode; the communication module integrates a plurality of communication protocols and interfaces, and dynamically selects an optimal communication path and protocol according to a communication requirement and an environment; the storage module adopts a multi-level architecture design to realize a transactional write-in and power failure protection mechanism; the technical bottlenecks of insufficient computing power, difficult heterogeneous system cooperation and the like of an existing unmanned aerial vehicle are solved, the method is suitable for multiple scenes such as smart cities and emergency rescue, and the application efficiency of the unmanned aerial vehicle in multiple scenes is improved.

A computer-implemented method for power capacity planning of a computing system is disclosed, wherein the method comprises the following steps: a) assessing (S10) an activity of the computing system, wherein the activity comprises a number of program instances executed by the computing system and a load caused by the executed program instances; b) predicting (S12) an evolution of the activity based on the assessed activity by using a first machine learning algorithm (10) configured for activity evolution prediction; c) predicting (S14) a power consumption of the computing system as a first power metric based on the predicted activity evolution and by using a second machine learning algorithm (12) configured for power consumption prediction of the computing system; d) predicting (S16) an autonomy of one or more uninterruptible power supplies of the computing system as a second power metric based on the predicted power consumption and by using a third machine learning algorithm (12') configured for uninterruptible power supply autonomy prediction and receiving the power consumption prediction of the computing system as input; e) predicting (S18) a redundancy level of the computing system as a third power metric based on the predicted power consumption and a power architecture of the computing system; f) generating (S20) output data related to power capacity planning by processing the first, second and third power metrics.

The application discloses a software quality evaluation method based on CPU-GPU computing power benchmark, and relates to the technical field of software performance testing.The application firstly builds a standardized pure test environment, calibrates the theoretical peak value and the measured peak computing power of CPU and GPU as a benchmark reference, sets three types of test scenes of steady-state load, long-time continuity and resource limitation, synchronously collects core operation data at a fixed frequency, filters effective data through median filtering and steady-state deviation verification, then decomposes secondary quantitative indicators from three core dimensions of execution efficiency, operation stability and computing power adaptability, calculates the scores of each dimension after all normalization and weighting, finally obtains a software comprehensive quality score and completes grade division, and then automatically locates the bottleneck dimension and outputs the targeted optimization direction, so that the software quality under the heterogeneous computing power architecture can be quantified, reproduced and systematically evaluated.

The invention provides a collaborative management method for a high-computing-power terminal of an energy storage power station, and the method comprises the steps: carrying out the physical integration of a processor calculation unit and a storage unit, building a high-computing-power architecture, and building the high-computing-power terminal of the energy storage power station; an algorithm model is built on the high-computing-power architecture, and cooperation with the high-computing-power architecture is achieved by optimizing the algorithm model; a terminal intelligent management system is constructed based on the high-computing-power terminals, centralized management is carried out on the distributed high-computing-power terminals, algorithm models and data, and end-side cloud collaboration is achieved; the storage and calculation integrated high-computing-power architecture effectively breaks through a memory wall and a power consumption wall, reduces data transmission delay and energy consumption, and remarkably improves the calculation efficiency; through collaborative optimization of an energy storage algorithm and a high computing power architecture, and through an adaptive algorithm model and a data transmission design, the calculation acceleration performance is improved, and meanwhile, the data precision is ensured; the intelligent management system of the energy storage power station terminal improves the intelligent management level of the energy storage power station, and ensures the safety and stability of the operation of the power station.

The invention discloses an electric power architecture automatic generation method based on machine vision. The method comprises the following steps: collecting and preprocessing an electric power field image; executing power equipment target detection to obtain a power equipment candidate set; pixel-level contours of the candidate power equipment are obtained by using the improved SETR model, and a target power equipment set is obtained; topological feature extraction is executed to form structured topological feature data; generating a power equipment connection relation matrix; constructing a power architecture topology model; generating a power architecture diagram; the electric power architecture diagram is output in the image file format and the engineering design file format, automatic generation from the electric power field image to the electric power architecture diagram is achieved, and the electric power equipment recognition precision and the accuracy and efficiency of electric power architecture topology modeling are improved.

Apparatus and associated methods relate to a modular energy conversion system (MECS). In an illustrative example, the MECS may include a distributed power converter having a first and second subsets of hybrid converter modules (HCMs). For example, output ports of the first subset of HCMs may be electrically connected in series to form an upper arm, and the output ports of the second subset of HCMs may be electrically connected in series to form a lower arm. The upper and lower arms may be electrically connected at a first end to form a connection point. A unipolar voltage source may be electrically connected to an opposite end of the connection point of the upper and lower arms. A power combiner unit (PCU) may be physically separated from and electrically connected to the connection point. For example, the PCU may be configured to measure electrical property at the connection point and adaptively regulate AC power generated at the connection point based on the measured electrical property. Various embodiments may advantageously enable efficient integration of distributed renewable energy sources and energy storage while providing power scaling through a modular architecture.