6 results about "Power Architecture" patented technology

This invention provides a method and system for predicting vehicle speed in commercial vehicles using the E-Power architecture, relating to the field of commercial vehicle speed measurement technology. First, vehicle operating data is collected via hardwired and CAN bus lines. Second, the PCA method is used to extract features from the collected vehicle operating data, obtaining variables highly correlated with vehicle speed, which serve as input to the speed prediction model, improving computational efficiency. Finally, a speed prediction model is established based on a recursive fuzzy neural network and a multi-step prediction strategy, achieving accurate prediction of vehicle speed during operation and improving fuel economy and driving comfort.

A method for managing power resource in an augmented reality (AR) device is described. In one aspect, the method includes configuring a low-power mode to run on a low-power processor of the AR device using a first set of sensor data, and a high-power mode to run on a high-power processor of the AR device using a second set of sensor data, operating, using the low-power processor, a low-power application in the low-power mode based on the first set of sensor data, detecting a request to operate a high-power application at the AR device, in response to detecting the request, activating the second set of sensors of the AR device corresponding to the high-power mode, and operating, using the high-power processor, a high-power application in the high-power mode based on the second set of sensors.

Smart Dual-Patient Acupuncture Machine with Regulated Power Architecture

To improve energy efficiency and safety during the operation of an elevator system (1), an electrical power architecture is proposed which includes as its central component a regenerative elevator frequency converter (2) configured to supply motor currents for an elevator motor (8) of the elevator system (1). This frequency converter (2) has an input-side AFE converter (5) capable of feeding energy back from a DC intermediate circuit (3) of the frequency converter (2), mediated via the AFE converter (5), into a building power grid (13) and / or into an input-side connected AC supply network (7), particularly in response to corresponding control signals or consumption information that the frequency converter (2) obtains from a smart meter (14) via a corresponding communication link (17).Furthermore, the architecture preferably also provides a regenerative energy source (11) which is electrically connected directly to the DC intermediate circuit (3) of the frequency converter (2) via a unidirectional electrical converter (12).

This application discloses a method, system, apparatus, and storage medium for generating a power tree. The method includes: acquiring power architecture information input by a user, the power architecture information including each load point and its corresponding load point parameters; sorting each load point according to a preset sorting rule to obtain a sorting result; matching each load point with a corresponding power type according to the sorting result and a preset power type determination rule to obtain several power nodes; constructing an initial power tree based on the hierarchical relationship of the power nodes; and selecting matching power devices from a device database according to device matching rules based on the voltage and current parameters of each power node in the initial power tree, and constructing a final power tree based on the power devices. This application reduces the reliance on personal experience through matching rules, thereby reducing design defects caused by experience differences and automating the process from parameter input to power tree generation.

A method for communicating test information, includes providing a data stream to a circuit block that is implemented on a semiconductor die, demultiplexing data channels from the data stream, multiplexing the data channels to obtain a modified data stream after test information collected from a plurality of sections of the circuit block has been inserted into one or more data channels allocated to at least one section of the circuit block by corresponding embedded distributed test (EDT) circuits implemented in the at least one section of the circuit block, and transmitting the modified data stream to another circuit block implemented on the semiconductor die.