52 results about "Power Architecture" patented technology

The invention discloses a distributed heterogeneous computing power reasoning task dynamic scheduling method and system. The system comprises a computing power architecture adaptation module, a task scheduling module, a model updating module, a capability service module, a dynamic scheduling module, a resource evaluation module and a state sensing module. The computing power architecture adaptation module is used for identifying and matching a local heterogeneous computing power architecture and a remote heterogeneous computing power architecture; the task scheduling module is used for selecting a proper computing power terminal from a distributed heterogeneous computing power environment; the model updating module is used for updating the AI model in real time; the capability service module is used for providing a unified AI model service calling interface; the dynamic scheduling module is used for dynamically allocating computing power resources; the resource evaluation module is used for monitoring and evaluating the state of the computing power resource; the state sensing module is used for monitoring the health state of the computing power node in real time and responding to a fault in time; the scheduling efficiency of computing power resource scheduling is improved, and stable operation of the reasoning task is guaranteed.

The invention provides a computing power scheduling method and device for model training, a computer storage medium and electronic equipment, and relates to the technical field of computers. Comprising the following steps: in response to a received training task request for a to-be-trained model, dividing the to-be-trained model into a plurality of first model subtasks; aiming at the target model subtask, determining a heterogeneous computing power unit of a target resource type corresponding to the target model subtask from a heterogeneous computing power architecture according to a pre-configured computing power mapping table; the computing power mapping table comprises a one-to-one correspondence relationship between each computing task and the heterogeneous computing power unit of the corresponding resource type; and determining a target heterogeneous computing power unit from heterogeneous computing power units of the target resource type of each computing node in the heterogeneous computing power architecture, and allocating the target model subtask to the target heterogeneous computing power unit, so as to execute the target model subtask based on the target heterogeneous computing power unit. The method can improve the model training efficiency and the accuracy of the model prediction result.

The invention discloses a whole vehicle power hardware-in-the-loop simulation test system and method under a P2.5 + P4 hybrid architecture. The whole vehicle power hardware-in-the-loop simulation test system comprises a controller, a test cabinet and an upper computer system, the hybrid power gearbox control system is electrically connected with the high-voltage control system; the test cabinet is electrically connected with the hybrid power gearbox control system, the high-voltage control system and the upper computer system; the upper computer system comprises a management module, a signal interface module, a controller interface module and a virtual simulation vehicle module, the management module is connected with the test cabinet and the signal interface module, and the signal interface module is used for realizing signal interaction between the controller interface module and the management module; the controller interface module is connected with the signal interface module, the Soft ECU module and the power simulation module. Standardized development of the power simulation test system is realized, the modular design supports rapid adaptation of different vehicle type platforms and power architectures, and repeated development is reduced.

The invention discloses an embedded AI intelligent computing power architecture method, and particularly relates to the technical field of artificial intelligence processing architecture. Collecting a resource state parameter set R of the embedded device; obtaining a to-be-executed AI task set T, wherein each task comprises model complexity, real-time requirements, expected response duration and priority; constructing a computing power resource allocation evaluation function F based on R and T, and outputting a task scheduling priority score; allocating tasks to the embedded AI module according to the allocation scheme and executing reasoning; the resource state is dynamically monitored in the task running process, and if it is predicted that resources are about to be overloaded, a scheduling function F is triggered to reconstruct a resource allocation scheme; performing iterative optimization on weight parameters in the function F based on task history feedback; by means of the method and device, optimal adaptation of multi-task concurrent scheduling can be achieved under the condition that resources are limited, the computing power resource utilization rate, the response efficiency and the system stability are improved, and the method and device are suitable for various edge side AI scenes.

A method for managing power resources in an augmented reality (AR) device is described. In one aspect, the method includes configuring a low power mode to operate on a low power processor of the AR device using a first set of sensor data, and configuring a high power mode to operate on a high power processor of the AR device using a second set of sensor data, the method includes operating a low-power application in a low-power mode based on a first set of sensor data using a low-power processor, detecting a request to operate a high-power application at the AR device, activating a second set of sensors of the AR device corresponding to the high-power mode in response to detecting the request, and transmitting the second set of sensors to the low-power processor. And operating, using the high-power processor, the high-power application in a high-power mode based on the second set of sensors.

A method for managing power resource in an augmented reality (AR) device is described. In one aspect, the method includes configuring a low-power mode to run on a low-power processor of the AR device using a first set of sensor data, and a high-power mode to run on a high-power processor of the AR device using a second set of sensor data, operating, using the low-power processor, a low-power application in the low-power mode based on the first set of sensor data, detecting a request to operate a high-power application at the AR device, in response to detecting the request, activating the second set of sensors of the AR device corresponding to the high-power mode, and operating, using the high-power processor, a high-power application in the high-power mode based on the second set of sensors.

A method for managing power resource in an augmented reality (AR) device is described. In one aspect, the method includes configuring a low-power mode to run on a low-power processor of the AR device using a first set of sensor data, and a high-power mode to run on a high-power processor of the AR device using a second set of sensor data, operating, using the low-power processor, a low-power application in the low-power mode based on the first set of sensor data, detecting a request to operate a high-power application at the AR device, in response to detecting the request, activating the second set of sensors of the AR device corresponding to the high-power mode, and operating, using the high-power processor, a high-power application in the high-power mode based on the second set of sensors.

A power architecture that uses an efficient intermediate power conversion stage between AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that have low residency in high-power states. The sustained high-power rails are placed under an intermediate power conversion topology which is directly powered by the adaptor. The rest of the rails along with charging of the battery are powered by the battery charger.

This invention provides a method and system for predicting vehicle speed in commercial vehicles using the E-Power architecture, relating to the field of commercial vehicle speed measurement technology. First, vehicle operating data is collected via hardwired and CAN bus lines. Second, the PCA method is used to extract features from the collected vehicle operating data, obtaining variables highly correlated with vehicle speed, which serve as input to the speed prediction model, improving computational efficiency. Finally, a speed prediction model is established based on a recursive fuzzy neural network and a multi-step prediction strategy, achieving accurate prediction of vehicle speed during operation and improving fuel economy and driving comfort.

Systems and methods are described for applying one or more frequency domain analyses to AC components to automatically discriminate between different operating conditions of the power architecture. Embodiments can then adaptively adjust the voltage (e.g., and current) to reduce or eliminate extra power consumption based on the detected operating condition. In some embodiments, the frequency domain analyses are based on fast Fourier transform (FFT) techniques and / or total harmonic distortion (THD) techniques. Embodiments can be applied to internal power modules and / or to external power adapters.

The application relates to the technical field of cloud computing resource allocation, and discloses a heterogeneous computing power cooperative allocation method and system, which comprises the following steps: S1, characteristic modeling is performed on all-network heterogeneous computing power nodes in advance, a heterogeneous computing power characteristic matrix M containing computing power architecture types, available computing power scales, current load rates, available bandwidths, local storage reserves and real-time power consumptions is constructed, wherein the heterogeneous computing power nodes include four types of heterogeneous resource nodes, namely, general-purpose CPUs, general-purpose GPUs, AI acceleration NPUs and edge computing nodes; the application constructs a multi-dimensional quantitative heterogeneous adaptation model, three quantitative calculation formulas are introduced to respectively realize the calculation of an adaptation score, a total allocation cost and a dynamic correction coefficient, multiple optimization targets, such as architecture adaptability, power consumption, time delay, migration overhead and computing power fragmentation, are included in the allocation model, the accurate matching of the heterogeneous computing power nodes and to-be-allocated tasks can be realized, the performance advantages of different architecture heterogeneous computing powers can be fully exerted, and the overall computing power resource utilization rate can be effectively improved.

According to at least one aspect of the disclosure, a uninterruptible power supply includes a first input configured to be coupled to, and receive main power from, a main power source, a second input configured to be coupled to, and receive backup power from, a backup power source, an output configured to be coupled to at least one load, at least one current sensor, a four-quadrant inverter coupled to the first input, the second input, and the output, and at least one controller configured to control the four-quadrant inverter to provide power derived from the first input to the second input to charge the backup power source, and provide power derived from the second input to the output to supplement the main power.

A system (100) includes an air conditioning system including a first unit (200) including a compressor (242) and a second unit (250); an energy storage device (240); a first transfer switch providing a power connection to the first unit; and a system energy manager configured to control the first transfer switch to supply power to both the second unit and the first unit from one of an AC power grid (302) or the energy storage device.

A method for managing power resource in an augmented reality (AR) device is described. In one aspect, the method includes configuring a low-power mode to run on a low-power processor of the AR device using a first set of sensor data, and a high-power mode to run on a high-power processor of the AR device using a second set of sensor data, operating, using the low-power processor, a low-power application in the low-power mode based on the first set of sensor data, detecting a request to operate a high-power application at the AR device, in response to detecting the request, activating the second set of sensors of the AR device corresponding to the high-power mode, and operating, using the high-power processor, a high-power application in the high-power mode based on the second set of sensors.

The invention discloses a DSC decoder low-power-consumption architecture implementation method applying a power consumption dynamic isolation technology. A code stream pre-analysis unit, a BP vector pre-search unit, a P mode power consumption control unit used for dynamically isolating P mode power consumption and an ICH behavior simulation unit used for dynamically isolating I mode power consumption are included. The power consumption in the DSC decoding process mainly comes from prediction reconstruction in a P mode and coding index updating in an I mode, so that the power consumption of the P mode and the power consumption of the I mode of a decoder are dynamically isolated to achieve accurate power consumption control optimization. And the power consumption of the DSC decoder is obviously reduced.

Smart Dual-Patient Acupuncture Machine with Regulated Power Architecture

A structure may include a set of metal layers disposed on a substrate layer, where a dielectric material is disposed between adjacent metal layers in the set of metal layers. The structure may include a first superconducting structure and a second superconducting structure created in a metal layer selected from the set of metal layers. The first superconducting structure may have a first length along a first direction which is parallel to a primary routing direction of the metal layer, a second length along a second direction which is parallel to the substrate layer and perpendicular to the first direction, and a third length along a third direction which is directed away from the substrate layer and perpendicular to the first direction and the second direction. The third length may be greater than the second length.

Apparatuses and methods of capacitance-to-digital code conversion are described. One capacitance-to-digital converter (CDC) includes front-end circuitry, including a comparator. The CDC further includes a first capacitive digital-to-analog converter (CDAC) coupled to a first input of the comparator and, in a first phase, to a sensor cell. The CDC further includes a second CDAC coupled to a second input of the comparator and, in a second phase, to the sensor cell. The front-end circuitry provides a digital output. The digital output is proportional to a sensor capacitance of the sensor cell.

The invention discloses a modular digital variable inductance device based on coarse and fine coordinated modulation and a control method thereof, and belongs to the technical field of power electronic magnetic elements. The invention provides a digital variable inductor module integrating a hybrid magnetic circuit topology and an embedded control unit in order to solve the problems that the adjustment range and the adjustment precision of a traditional variable inductor are difficult to consider at the same time and direct interaction with a digital control system is difficult. According to the module, the topology that a multi-magnetic-core-section discrete inductance adjustment unit (coarse adjustment) and a magnetic control continuous inductance adjustment unit (fine adjustment) are connected in series is adopted on a power framework, and an externally input digital or analog inductance demand instruction is analyzed into a hierarchical control signal through a built-in microcontroller on a control framework. Stepless, smooth and high-precision adjustment of an inductance value in a wide range is realized through large-span step switching of the coarse adjustment unit and linear interpolation compensation of the fine adjustment unit.

An electronic device may include a printed circuit board. The electronic device may include a first core with a first cavity, the first core formed from an organic material, and the first cavity configured to house a DC capacitor for delivery of direct current to a die from a voltage source. The device may include a second core with a second cavity, the second core formed from an inorganic material and the second cavity configured to house an AC capacitor coupled to an output of the die for decoupling alternating current effects associated with the direct current. The device may include an interposer layer disposed between the first core and the second core, configured to isolate the first core and the second core.

The invention discloses a multi-layer intermediate representation compiler implementation method based on RISC-V open source chip hardware perception, and belongs to the technical field of computer systems and compilation. The method comprises the steps that hardware feature data are acquired, and a hardware feature database is formed; a hierarchical controllable IR exposure mechanism is adopted, and according to hierarchical intermediate representation and a hardware feature database, an intra function related source code for specific hardware feature data is generated based on a three-level general computing power architecture of an RISC-V open source chip instruction set and an extended instruction set; and compiling the scalar-related source code and the intra-function-related source code in the user source code into an executable file or a binary library by using a general compiler, or compiling the intra-function-related source code into the executable file or the binary library by using the general compiler. The multi-layer intermediate representation compiler implementation method based on RISC-V open source chip hardware perception can quickly adapt to a novel chip and closely fit hardware, and efficient, super-heterogeneous and super-parallel code generation is achieved.

To improve energy efficiency and safety during the operation of an elevator system (1), an electrical power architecture is proposed which includes as its central component a regenerative elevator frequency converter (2) configured to supply motor currents for an elevator motor (8) of the elevator system (1). This frequency converter (2) has an input-side AFE converter (5) capable of feeding energy back from a DC intermediate circuit (3) of the frequency converter (2), mediated via the AFE converter (5), into a building power grid (13) and / or into an input-side connected AC supply network (7), particularly in response to corresponding control signals or consumption information that the frequency converter (2) obtains from a smart meter (14) via a corresponding communication link (17).Furthermore, the architecture preferably also provides a regenerative energy source (11) which is electrically connected directly to the DC intermediate circuit (3) of the frequency converter (2) via a unidirectional electrical converter (12).

A gate ground (GTD) cell utilizing a backside power delivery scheme is disclosed in which metal lines that deliver power are disposed on the backside of a wafer. Thus, an ultra-low height standard cell may be implemented. And relatively high area miniaturization can be realized. In addition, performance and power gain may be maximized.

This application discloses a method, system, apparatus, and storage medium for generating a power tree. The method includes: acquiring power architecture information input by a user, the power architecture information including each load point and its corresponding load point parameters; sorting each load point according to a preset sorting rule to obtain a sorting result; matching each load point with a corresponding power type according to the sorting result and a preset power type determination rule to obtain several power nodes; constructing an initial power tree based on the hierarchical relationship of the power nodes; and selecting matching power devices from a device database according to device matching rules based on the voltage and current parameters of each power node in the initial power tree, and constructing a final power tree based on the power devices. This application reduces the reliance on personal experience through matching rules, thereby reducing design defects caused by experience differences and automating the process from parameter input to power tree generation.

The invention discloses a power supply virtualization management system based on a microkernel mechanism, and relates to the technical field of interface management, a Hypervisor power supply virtualization architecture and a mail-box mechanism reduce faults, are of great significance to key businesses of an enterprise data center, can avoid interruption of businesses such as financial transactions and an ERP system, and a CPU frequency modulation and Thermal regulation and control module ensures system stability under different working conditions, so that the power supply virtualization management system has a good application prospect. A mail-box mechanism reduces the hardware updating risk and ensures that services are not stopped, a Hypervisor power supply architecture optimizes power supply management, the efficiency is improved through interaction of a User OS and a ServiceOS, the energy cost is reduced, the server performance is ensured, the service process is accelerated, and the office efficiency is improved. CPU frequency modulation and a Thermal regulation strategy balance performance and power consumption to meet requirements of different departments, a mail-box mechanism ensures security isolation, prevents information leakage in a multi-system environment, protects core data, ensures security of sensitive data such as data center finance and the like, a CPU hot plug mechanism prevents hardware and data problems, the mail-box mechanism ensures instruction transmission and execution in an industrial automation scene, and the safety of the industrial automation scene is ensured. And the production efficiency and quality are improved.

Apparatus and associated methods relate to a modular energy conversion system (MECS). In an illustrative example, the MECS may include a distributed power converter having a first and second subsets of hybrid converter modules (HCMs). For example, output ports of the first subset of HCMs may be electrically connected in series to form an upper arm, and the output ports of the second subset of HCMs may be electrically connected in series to form a lower arm. The upper and lower arms may be electrically connected at a first end to form a connection point. A unipolar voltage source may be electrically connected to an opposite end of the connection point of the upper and lower arms. A power combiner unit (ECU) may be physically separated from and electrically connected to the connection point. For example, the PCU may be configured to measure electrical property at the connection point and adaptively regulate AC power generated at the connection point based on the measured electrical property. Various embodiments may advantageously enable efficient integration of distributed renewable energy sources and energy storage while providing power scaling through a modular architecture.

The invention discloses a teaching cloud disk data processing method based on an AI computing power architecture, and relates to the technical field of teaching cloud disk data protection, and the method comprises the following steps: obtaining data needing security protection in a teaching cloud disk, and naming the data as private data; performing textualization processing on the image data, and naming the image data after textualization processing as textualized data; calculating the text data and the textualized data through a privacy security protection algorithm to obtain privacy security data; performing secure storage on the privacy security data; when the user accesses the privacy security data, verifying the identity information of the user and the user permission; the method is used for solving the problems that the consumption of computing resources is increased and the data is easy to steal and crack due to insufficient universality of protection of data in different formats and insufficient protection means of the data in the existing teaching cloud disk data protection technology.

The invention discloses an integrated power supply framework, a power supply system and a vehicle, which are characterized in that an accessed first voltage is converted into a second voltage through a first voltage conversion circuit to charge a power battery pack, or the second voltage provided by the power battery pack is converted into the first voltage to be output; the second voltage conversion circuit converts a second voltage provided by the first voltage conversion circuit or the power battery pack into a third voltage, and the power supply distribution circuit receives the third voltage and distributes electric energy to a plurality of load power supply ends; the first voltage conversion circuit, the second voltage conversion circuit and the power supply distribution circuit share the same controller, so that the functions of vehicle-mounted charging and discharging and low-voltage distribution are integrated in vehicle power supply, the integration level of the system is improved, the response time of each functional circuit is reduced, the use of wire harnesses, connectors and the like is reduced, and the cost is reduced.

The invention discloses a two-stage power supply architecture and a cooperative control method thereof. The two-stage power supply architecture comprises a first-stage converter, a second-stage converter, a first-stage controller and a second-stage controller, the first-stage converter receives voltage input by an external input bus and outputs intermediate bus voltage to the second-stage converter; the second-stage converter outputs the converted voltage to the second-stage controller and external load equipment; the second-stage controller further receives an externally input reference voltage, controls the working state of the second-stage converter based on the converted voltage and the reference voltage and outputs the current local working state to the first-stage controller, and the first-stage controller further receives an externally input reference working state and controls the working state of the second-stage converter based on the reference working state. And the working state of the first-stage converter is controlled based on the reference working state and the current local working state to ensure that the two-stage power supply architecture works at the optimal efficiency point. The power supply has the characteristics of high efficiency and high transient response.

Embodiments disclosed herein relate to a split rail power architecture, and more particularly, to providing isolation and control of the power supply via power management circuitry. In an example, an integrated circuit device is provided that includes: a device voltage supply (VDS) (105); an input / output (I / O) voltage supply (VDDIO) (106) coupled to the VDDS (105); and a level shifter circuit (115) coupled to the VDDIOs (106). The level shifter circuit (115) includes: a pair of cross-coupled PMOS transistors (116 and 118); a pair of NMOS transistors (117 and 119) coupled between the PMOS transistors (116 and 118) and a ground connection (114); and an inverter circuit (110) coupled to the VDDS (105) and the level shifter circuit (115). The level shifter circuit (115) further includes a capacitor (120) coupled to the PMOS transistors (116 and 118) and the ground connection (114) and in parallel with respect to the NMOS transistor (117).