Novel 12-tube SRAM (Static Random Access memory) unit circuit capable of simultaneously increasing read noise tolerance and writing margin

A noise tolerance, unit circuit technology, applied in the field of circuits, can solve problems such as extra power consumption, stability damage, etc., to achieve the effect of improving write margin, eliminating half-select problems, and solving write-half-select problems

Active Publication Date: 2015-01-21
ANHUI UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The purpose of the present invention is to provide a novel 12-tube SRAM unit circuit that improves read noise tolerance and write margin simultaneously, solves the problem of extra

Method used

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  • Novel 12-tube SRAM (Static Random Access memory) unit circuit capable of simultaneously increasing read noise tolerance and writing margin
  • Novel 12-tube SRAM (Static Random Access memory) unit circuit capable of simultaneously increasing read noise tolerance and writing margin
  • Novel 12-tube SRAM (Static Random Access memory) unit circuit capable of simultaneously increasing read noise tolerance and writing margin

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Embodiment

[0032] Figure 4 It is a schematic structural diagram of a novel 12-tube SRAM unit circuit that improves read noise tolerance and write margin at the same time provided by an embodiment of the present invention. like Figure 4 As shown, the circuit mainly includes:

[0033] Four PMOS transistors P1~P4 and eight NMOS transistors N1~N8;

[0034] Wherein, the NMOS transistor N1 and the PMOS transistor P1 form an inverter A1, the input terminal of the inverter A1 is connected to the word line WL, the output terminal is connected to the gate of the NMOS transistor N4, and the source of the PMOS transistor P1 is connected to the chip selection CS , the source of the NMOS transistor N1 is grounded;

[0035] The PMOS transistor P4 and the NMOS transistor N7 form a parallel structure, and the gate of the NMOS transistor N7 is connected to the word line WL;

[0036] NMOS transistor N2 and PMOS transistor P2 form an inverter A2, and NMOS transistor N3 and PMOS transistor P3 form an i...

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Abstract

The invention discloses a novel 12-tube SRAM (Static Random Access memory) unit circuit capable of simultaneously increasing read noise tolerance and writing margin, and the novel 12-tube SRAM unit circuit can eliminate a partial-select problem and solve a read partial-select problem and a writing partial-select problem, a stability problem cannot be caused, and additionally, no additional power is consumed. Experiments measure that compared with a traditional 6T unit, the read dynamic power consumption and the writing dynamic power consumption of an array with the total number of 128 are respectively reduced by 81.3% and 88.2% when a column decoding unit (CMUX) is 4; additionally, according to the circuit, the read noise tolerance is greatly increased, so that the read noise tolerance is similar to the noise tolerance in a hold mode and reaches 2.3 times of that of the traditional 6T unit; in addition, according to the circuit, a feedback structure of a phase inverter is interrupted, so that the writing margin is increased and reaches 1.41 times of that of a traditional 6T SRAM unit.

Description

technical field [0001] The invention relates to the technical field of circuits, in particular to a novel 12-tube SRAM unit circuit which simultaneously improves read noise tolerance and write margin. Background technique [0002] High speed and low power consumption are the focus of today's SRAM (Static Random Access Memory) design, while improving a certain performance may affect another performance to make it worse. With the continuous reduction of process size, the continuous decrease of power supply voltage and the increase of storage capacity, the soft error rate of memory will become higher and higher, and the reliability and yield of SRAM are facing challenges. However, traditional error correction coding (ECC) can only solve single-bit soft errors. When the process node enters the nanoscale, the probability of multi-bit soft errors will increase exponentially. To solve this problem, bit-interleaved array structures are widely used. However, the use of the bit inte...

Claims

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Application Information

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IPC IPC(8): G11C11/419
CPCG11C11/419
Inventor 李正平闫锦龙卢文娟陶有武彭春雨谭守标陈军宁周永亮
Owner ANHUI UNIVERSITY
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