Semiconductor storage, semiconductor device and semiconductor device control method

Abstract

A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

Description

[0001] This application is a divisional application of the invention patent application with the application number 99101611.4 and the invention name "semiconductor memory" submitted by Hitachi Manufacturing Co., Ltd. on January 28, 1999. technical field [0002] The present invention relates to a semiconductor memory, a semiconductor device and a control method for the semiconductor device. Background technique [0003] In conventional technology, nonvolatile memories such as flash EEPROMs have been obtained using MOSFETs having a floating gate and a control gate. In this device, information storage and readout are performed using the principle that the MOSFET threshold voltage changes when carriers are accumulated on the floating gate. [0004] Polysilicon is commonly used in floating gates. Using a MOSFET with a floating gate, only one transistor can be used to store information over a long period of time. As examples of flash EEPROM memory cell structures, Nikkei Elect...

AI Technical Summary

Problems solved by technology

The open structure has the advantage that the memory cells can be located at all intersections of the data line and the word line and can achieve high integration, but the disadvantage is that it will generate much larger noise in the word line

On the contrary, the advantage of the folded structure is that the noise generated when driving the word line is small, but its disadvantage is that the memory cells cannot be located at all intersections of the data line and the word line, so that it cannot provide high integration

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