Storage unit circuit with adaptive leakage current cutoff mechanism

A memory cell circuit, leakage current technology, applied in information storage, static memory, digital memory information and other directions, can solve the problems of increased static energy consumption of memory banks, reduced product life and reliability, etc., to reduce leakage power consumption, The effect of low power consumption and high robustness

Inactive Publication Date: 2011-09-07
SOUTHEAST UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Considering the large number of transistors in the memory bank, the static energy consumption of the

Method used

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  • Storage unit circuit with adaptive leakage current cutoff mechanism
  • Storage unit circuit with adaptive leakage current cutoff mechanism
  • Storage unit circuit with adaptive leakage current cutoff mechanism

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Embodiment Construction

[0027] see figure 1 , the memory unit circuit with low power consumption and high robustness of the present invention with adaptive leakage current cut-off mechanism is composed of twelve transistors: four PMOS transistors P1, P2, P3, P4 and eight NMOS transistors N1~N8 , the transistor constitutes a double-terminal read-write sub-threshold memory cell circuit, and the memory cell circuit is connected between the bit line BL and the bit line between.

[0028] Among them, the body terminals of the four PMOS transistors are connected to the power supply voltage Vdd, and the body terminals of the eight NMOS transistors are grounded; the drain terminal and the gate terminal of the NMOS transistor N1 are respectively connected with the drain terminal and the gate terminal of the PMOS transistor P1, forming the first An inverter; the drain terminal and the gate terminal of the NMOS transistor N2 are respectively connected with the drain terminal and the gate terminal of the PMOS t...

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Abstract

The invention provides a storage unit circuit with an adaptive leakage current cutoff mechanism, which is a dual-port read-writing sub-threshold storage unit circuit. The circuit comprises a first inverter and a second inverter which are connected in a cross coupling way; the two inverters are connected between complementary bit lines through an equalizer pipe; and the grid end of the equalizer pipe is connected with an enhanced word line. The invention overcomes the defects of the prior art and provides the sub-threshold storage unit circuit with low power consumption and high robustness; and the sub-threshold storage unit circuit can reduce leakage power consumptions in dynamic operation and static operation while the leakage power at the same time on the premise of not increasing dynamic power consumption or reducing performance, and can balance each index of a storage unit so as to optimize system performance.

Description

technical field [0001] The invention relates to a low-power storage unit under a sub-threshold working region in a sub-threshold design, in particular to a sub-threshold storage unit circuit with an adaptive leakage current cut-off mechanism, which can be used without an adaptive leakage current cut-off mechanism. Under the premise of increasing dynamic power consumption and not reducing performance, the leakage power consumption in dynamic operation and static operation can be reduced at the same time, and it has the characteristics of high robustness. Background technique [0002] Memory cell arrays are an important part of modern digital systems, and are often the bottleneck of power consumption in system design. The continuous improvement of the market's demand for various portable devices puts forward higher requirements for the power consumption reduction technology of the memory cell array. Sub-threshold design is currently a hot topic in ultra-low power design. By ...

Claims

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Application Information

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IPC IPC(8): G11C11/56
Inventor 杨军柏娜吴秀龙朱贾峰仇名强
Owner SOUTHEAST UNIV
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