37results about How to "Improve writing ability" patented technology

Embodiments of the invention provide a perpendicular magnetic recording medium that not only attains the magnetic isolation of crystal grains in a magnetic recording layer from one another in a region of the medium in which the thickness of an intermediate layer is equal to or smaller than about 20 nm but also exhibits excellent crystallographic texture and that exhibits small medium noise, excellent thermal stability, and high write-ability. In one embodiment, a perpendicular magnetic recording medium has at least a soft-magnetic underlayer, a first intermediate layer, a second intermediate layer, a third intermediate layer, and a magnetic recording layer successively formed on a substrate. The magnetic recording layer is composed of ferromagnetic crystal grains and oxides or nitrides, the third intermediate layer is composed of Ru or an Ru alloy, the second intermediate layer is composed of a metal or an alloy having the face-centered cubic lattice structure, and the first intermediate layer is composed of a metal or an alloy having the hexagonal close-packed structure.

The invention provides a storage unit circuit with an adaptive leakage current cutoff mechanism, which is a dual-port read-writing sub-threshold storage unit circuit. The circuit comprises a first inverter and a second inverter which are connected in a cross coupling way; the two inverters are connected between complementary bit lines through an equalizer pipe; and the grid end of the equalizer pipe is connected with an enhanced word line. The invention overcomes the defects of the prior art and provides the sub-threshold storage unit circuit with low power consumption and high robustness; and the sub-threshold storage unit circuit can reduce leakage power consumptions in dynamic operation and static operation while the leakage power at the same time on the premise of not increasing dynamic power consumption or reducing performance, and can balance each index of a storage unit so as to optimize system performance.

A perpendicular magnetic recording medium includes a nonmagnetic substrate; a first underlayer provided on the nonmagnetic substrate; a first nonmagnetic intermediate layer provided on the first underlayer; a second underlayer provided on the first nonmagnetic intermediate layer; a second nonmagnetic intermediate layer provided on the second underlayer; and a magnetic recording layer provided on the second nonmagnetic intermediate layer, wherein the first underlayer comprises a soft magnetic material which has a face-centered cubic structure and which includes at least Ni and Fe, and wherein the second underlayer comprises a soft magnetic material which has a face-centered cubic structure and which includes at least Co. The orientation dispersion is reduced and crystal grain diameters are smaller in the magnetic recording layer, and the film thickness of nonmagnetic intermediate layers can be decreased so that performance improvements such as reduced noise, increased S/N ratio, and improved write-ability are achieved.

A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

The invention discloses a single-end-operated subthreshold storage unit circuit, comprising two PMOS (P-channel Metal Oxide Semiconductor) transistors, namely P1 and P2, and seven NMOS (N-channel Metal Oxide Semiconductor) transistors, namely N1-N7, wherein the body ends of P1 and P2 are connected with a voltage drain-drain Vdd after being connected with the respective sources; the body ends of N1-N7 as well as the sources of N1, N2 and N7 are all grounded; the grid of N3 is connected with a row-writing control signal RWR; the grid of N4 is connected with a column-writing control signal CWR; an inverter is composed of N2 and P2; the output end of the inverter is connected with the grids of N2 and P2; the input end of the inverter is connected with the drain of P1; the grid of the N5 is connected with a reading word line RWL; the drain of N5 is connected with a reading bit line RBL; the source of N6 is connected with a writing bit line WBL; and the grid of N6 is connected with a word writing line WWL.

A magnetic recording medium includes a non-magnetic substrate on which at least a soft magnetic underlayer, an orientation control layer, a perpendicular magnetic layer, and a protective layer are disposed. The perpendicular magnetic layer includes first to fourth magnetic layers. A first exchange coupling control layer is disposed between the first magnetic layer and the second magnetic layer. A second exchange coupling control layer is disposed between the second magnetic layer and the third magnetic layer. Following relations are satisfied where Ku_i is a magnetic anisotropic constant of an i-th magnetic layer, Ms_i is a saturation magnetization of the i-th magnetic layer, and t₁ is a film thickness of the i-th magnetic layer, Ku₁>Ku₂, Ku₂>Ku₃, Ms₁×t₁>Ms₂×t₂, Ms₂×t₂>Ms₃×t_{3 r} Ku₃<Ku₄, and Ms₃×t₃<Ms₄×t₄.

An SRAM (Static Random Access Memory) storage unit circuit capable of realizing high read-write stability under low voltage is of a nine-tube structure, a grid electrode of a sixth NMOS (N-channel Metal Oxide Semiconductor) tube is connected with a grid electrode of a fifth NMOS tube and a first writing line, a drain electrode of the sixth NMOS tube is connected with a writing bit line, and a source electrode of the sixth NMOS tube is connected with a drain electrode of the fifth NMOS tube; the grid electrode of the second NMOS tube is connected with a third writing line, the drain electrode of the second NMOS tube is connected with the source electrode of the fifth NMOS tube, the drain electrode of the first PMOS tube and the grid electrodes of the third PMOS tube, the third NMOS tube andthe fourth NMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the second PMOS tube is connected with the second writing line, the drain electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube, and the source electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube and the power supply voltage; the drain electrode of the third NMOS transistor is connected with the drain electrode of the third PMOS transistor and the grid electrodes of the first NMOS transistor and the first PMOS transistor, and the source electrode of the third NMOS transistor is connected with the source electrode of the first NMOS transistor and the ground; and the drain electrode of the fourth NMOS transistor is connected with a read bit line, and the source electrode is connected with a read word line. The method can improve the writing capability of the SRAM storage unit, reduces the static power consumption of the system, does not affect the reading stability, and is especially suitable for low-voltage application.

The invention provides an intelligent composition correction method and system, and relates to the technical field of data processing. The intelligent composition correction method comprises the following steps: acquiring to-be-corrected composition information; enabling article content in the composition information to be corrected to be subjected to physical identification; extracting grade information in the to-be-corrected composition information and matching in a preset multi-dimensional evaluation standard according to the grade information and the article style in the to-be-corrected composition information; then, extracting and respectively adding each piece of dimension information in the matched multi-dimension evaluation standard into a preset score item plate and a lost score item plate; obtaining evaluation information of each dimension in the to-be-evaluated score item and the to-be-evaluated score item input by the user; and finally, generating a diagnosis and treatment type correction summary report according to the evaluation information of each dimension. Therefore, accurate detailed batch is realized, the correction result is more accurate, and the objectivity of composition correction is improved. The writing ability of students can be improved; teachers can conveniently master scientific and accurate correction compositions, and the service quality is improved.

Disclosed is a static random access memory including an assist circuit. More particularly, a static random access memory according to an embodiment of the present disclosure may include a bit cell part including at least one bit cell connected between a first ground voltage node and a second ground voltage node; and a controller including a first transistor configured to control connection between the first ground voltage node and the second ground voltage node, a second transistor configured to float a first ground voltage of the first ground voltage node, and a third transistor configured to float a second ground voltage of the second ground voltage node, wherein the controller controls the first and second ground voltages supplied to the bit cell part using the first, second, and third transistors.