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Near-threshold 8-tube static random memory unit

A memory unit, static random technology, applied in the topological structure design of the new static random memory unit, the unique write ability enhancement scheme field, can solve the problem that the write operation ability has not been improved, the stability and speed of the write operation cannot meet the standard, etc.

Inactive Publication Date: 2015-09-02
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for the new structure, the write operation can only be performed on one side, that is, only one pass transistor is used for the write operation, coupled with the influence of the threshold voltage loss, the stability and speed of the write operation are far from the standard
For other new academic cell topologies, some combine the advantages of traditional 6-tube SRAM cells and 7-tube SRAM cells with bilateral write operations at the cost of sacrificing area, but the purpose of these structures is actually only to improve The read operation ability and data storage stability, the write operation ability has not been improved, and even some structures have improved the read ability and stability on the premise of sacrificing the write operation performance.

Method used

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  • Near-threshold 8-tube static random memory unit
  • Near-threshold 8-tube static random memory unit
  • Near-threshold 8-tube static random memory unit

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Embodiment

[0038] Provide a specific embodiment of the present invention below

[0039] This embodiment is an 8-tube SRAM unit with balanced reading and writing capabilities under a near-threshold working voltage and an area of ​​the same order of magnitude as the traditional 6-tube SRAM unit. The working voltage is 0.6V, and the process is 40nm.

[0040] The parameters of each tube: the N3 tube adopts the low-threshold tube under the 40nm process, and the other seven tubes adopt the high-threshold tube; all eight transistors adopt the minimum design size under the 40nm process;

[0041] Compared with the traditional 6-tube SRAM unit performance index simulation results:

[0042] The traditional 6-tube SRAM unit static noise tolerance (the amplitude of the maximum DC noise signal that the storage unit can bear) is only 0.0135V, and the 8-tube SRAM unit of this embodiment has 0.193V; the write noise tolerance (changing the data storage node L is the maximum bit line BL voltage of "0" sta...

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Abstract

The invention relates to a near-threshold 8-tube static random memory unit, and belongs to the field of design of integrated circuits. The unit structurally comprises a first phase inverter consisting of a first NMOS transistor and a first PMOS transistor, and a second phase inverter consisting of a second NMOS transistor and a second PMOS transistor; the input ends and output ends of the two phase inverters in serial connection are respectively connected with a source electrode and a drain electrode of a third PMOS transistor so as to form a latch structure; the source electrode and drain electrode of the third PMOS transistor are respectively connected with a bit line BL and a data storage point L; a grid electrode of the second NMOS transistor and a grid electrode of the third PMOS transistor are both connected to a write line WWL; a drain electrode and a source electrode of a fourth NMOS transistor are respectively connected with a bit line BR and a source electrode of a fifth NMOS transistor; a grid electrode of the fourth NMOS transistor is connected to a read line RWL; a grid electrode of the fifth NMOS transistor is connected to a data storage point R; the drain electrode of the fifth NMOS transistor is connected to ground gnd. The structure can be used for reinforcing the stability and the read and write capabilities of a near-threshold working voltage, and further reducing the power consumption, has no size construction of pull-down ratio and the like, is capable of simplifying the design difficulty further, and has no cost of area sacrifice.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and relates to a novel static random access memory (SRAM) cell topology design working at a near-threshold operating voltage, in particular to a novel read and write operation separation scheme and a unique write capability enhancement scheme of the structure . Background technique [0002] With the continuous improvement of MOS manufacturing process and the improvement of integration, the size of transistors becomes smaller and smaller. In the design of modern integrated circuits, the power consumption of circuits has become a huge challenge. Among the methods of reducing power consumption, the most direct method is to reduce the operating voltage. Enabling circuits to operate in the near-threshold region has become a development trend. [0003] Static random access memory (SRAM) is a key component of the current microprocessor, and its area, power consumption, and stability ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/416
Inventor 蒋承志叶佐昌王燕
Owner TSINGHUA UNIV
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