A New Testable Structure of Lookup Table

Abstract

The invention discloses a novel testability structure of a lookup table, which relates to the technical field of programmable logic devices. In the novel testability structure, the output port of the lookup table is connected to the input port of a flip-flop and the output signal of the lookup table is stored in In the flip-flop, the output port of the flip-flop is connected to the input port of the configuration storage unit through the transmission gate, and the test enable signal is connected to drive the on-off of the transmission gate; when the test enable signal is valid, the transmission gate is turned on and the flip-flop The output signal of the lookup table is written into the corresponding configuration storage unit, and the configuration readback circuit reads the output signal of the lookup table in the configuration storage unit to determine the function value of the lookup table to realize the test, the reading speed is faster, and the reading speed is improved. The acquisition efficiency and addressing and positioning capabilities, and because the boundary scan chain is canceled, it solves the problems of reducing the circuit operating frequency and increasing the difficulty of routing caused by the boundary scan chain.

Description

technical field [0001] The invention relates to the technical field of programmable logic devices, in particular to a novel testability structure of a lookup table. Background technique [0002] Programmable logic devices are the core industry of semiconductor integrated circuits. They have the characteristics of short development cycle, low cost, low risk, high integration, high flexibility, and easy maintenance and upgrade of electronic systems. They are widely used in automobiles, electronics, objects, etc. Networking, data centers, communications and medical equipment and many other fields. With the advancement of process dimensions and the emergence of VLSI, the scale of programmable logic devices has risen to tens of millions of gates and hundreds of millions of gates. [0003] However, due to the high integration, small size, large area, and multiple pins of programmable logic devices, testability design and chip testing have become a major problem in chip failure an...

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Problems solved by technology

However, the insertion of the boundary scan chain will increase the number of stages at the input of the flip-flop, so it will increase the propagation delay on the critical path and reduce the operating frequency of the circuit. At the same time, the boundary scan chain needs to be cascaded up and down in the form of a carry chain. It increases the difficulty of metal wiring of the circuit and increases the difficulty of wiring of the chip

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