Low power consumption static random memory with low level thread amplitude of oscillation

Abstract

Disclosed is a low power consumption static random memory with low level thread amplitude of oscillation, wherein the memory comprises a pre-charging circuit based on electric charge sharing, a memory unit, a line decoder, a row decoder, a selector, a read-write control circuit, a sensitive amplifier and an input processing circuit, wherein the bit line end of the pre-charging circuit is connected to the bidirectional port of the selector, the output end of the input treatment circuit is connected with the input end of the sensitive amplifier and the selector.

Description

technical field [0001] The invention relates to the design of a high-performance memory, which belongs to the technical field of integrated circuit manufacturing. Background technique [0002] With the continuous improvement of integrated circuit design technology and the strong demand of the electronic market, high-performance system-on-chip (SoC) emerged as the times require. In order to improve performance, a large amount of memory is usually embedded in the SoC, the area of ​​which is as high as 50%-60% of the entire SoC chip area, and the power consumption of the memory accounts for 25%-40% of the power consumption of the entire SoC chip. For embedded processors, Cache and on-chip RAM are usually embedded, and these are composed of SRAM (Static Random Access Memory). Therefore, the problem of SRAM power consumption has attracted more and more attention. [0003] The power consumption of SRAM is mainly composed of three parts. One is dynamic ...

AI Technical Summary

Problems solved by technology

One is dynamic power consumption, that is, the power consumption consumed by charging and discharging the capacitor

The second is short-circuit power consumption, that is, the power consumption consumed when the power supply and ground are turned on

The third is the static power consumption caused by the leakage current of the MOS tube

The bit line dynamic power consumed by the bit line swing of these memory cells is also very large

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