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Dynamic multi-clock low power consumption AHB bus design method for SOC

A technology of dynamic power consumption and design method, applied in energy-saving computing, energy-saving ICT, instruments, etc., to achieve the effect of reducing circuit power consumption

Active Publication Date: 2009-07-29
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The dynamic power consumption is mainly caused by charging and discharging the parasitic capacitance of the transistor

Method used

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  • Dynamic multi-clock low power consumption AHB bus design method for SOC
  • Dynamic multi-clock low power consumption AHB bus design method for SOC

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Experimental program
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Effect test

Embodiment

[0016] It mainly has the following two working states:

[0017] 1. When the master on the high-speed AHB bus accesses the slaves on the high-speed AHB bus, the AHB-AHB bridge does not work. At this time, the master on the low-speed AHB bus can also access the slaves on the low-speed AHB bus at the same time. The high-speed AHB bus and the low-speed AHB bus work at the same time to improve the working efficiency of the system

[0018] 2. When the master on the high-speed AHB bus accesses the slave on the low-speed AHB bus, we need to transmit data through the AHB-AHB bridge. First, the master of the high-speed AHB bus accesses the AHB-AHB bridge as a slave, and stores the transmitted data in the register of the AHB-AHB bridge; then the AHB-AHB bridge acts as a master of the low-speed AHB bus on its bus. slaves to access. Because the processing speed of the devices on the low-speed AHB bus is slow, when the AHB-AHB bridge operates as the host of the low-speed bus, it sends a s...

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Abstract

The invention relates to a design method of a dynamic multi-clock AHB bus with low power consumption used for SOC. The method adopts a multi-clock gating register to realize the control of clock signals of each module; when a certain module is needed to work, a corresponding grating signal is opened so as to lead the module to work normally; otherwise, the grating signal is closed, the clock does not work and then the dynamic turning of a logic gate can be reduced so as to achieve the purpose of reducing the system dynamic power consumption; moreover, an AHB-AHB bridge is adopted and a plurality of AHB buses can be adopted and then the high-speed and low-speed devices all can be connected with the different AHB buses; the AHB buses are mutually connected through the AHB-AHB bridge; and the clock frequency of certain modules can be reduced so as to achieve the purpose of reducing the dynamic power consumption.

Description

technical field [0001] The invention relates to the technical field of electronic circuit design, in particular to a design method of a dynamic multi-clock low-power AHB bus for SOC mainly aimed at the AHB bus. Background technique [0002] With the development of microelectronics technology, the complexity of the system is getting higher and higher. At the same time, the size of the semiconductor process is getting smaller and smaller, reaching the nanometer level. The number of transistors integrated per unit area is increasing, so the corresponding power consumption is also increasing. How to reduce the power consumption of the system has become a very important topic in today's IC design. [0003] In CMOS circuits, power consumption mainly includes static power consumption and dynamic power consumption. The static power consumption is mainly caused by the leakage current of the reverse-biased PN junction and the subthreshold current of the transistor. The main form is le...

Claims

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Application Information

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IPC IPC(8): G06F1/06G06F1/32G06F13/40
CPCY02B60/1228Y02B60/1235Y02D10/00
Inventor 李峰于治楼
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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