Router power consumption model based on network on chip

A network-on-a-chip, router technology, applied in the field of router power consumption model, can solve the problems of small computational complexity and implementation cost, increasing NoC cost, reducing network performance, etc.

Active Publication Date: 2008-07-23
NANJING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since a large number of routers exist in the NoC, in order to make the introduction of the power management mechanism not significantly increase the co...

Method used

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  • Router power consumption model based on network on chip
  • Router power consumption model based on network on chip
  • Router power consumption model based on network on chip

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Embodiment 1

[0058] A router power consumption model based on a network-on-chip, which simplifies the router operation into four power consumption links of write cache, read cache, span switch and span link according to the proportion of power consumption, and attributes the dynamic power consumption to the current The bit inversion activity triggered when the data piece arrives, the power consumption is counted through the bit inversion activity, and the obtained router

[0059] The power consumption model is as follows:

[0060] P total = ( C wr - bit × Σ i = 1 N fli t - wr ...

Embodiment 2

[0064] Using the statistical average value of the bit inversion number to replace the instantaneous sampling value, the simplified formula of the router power consumption model is as follows:

[0065] P total =(C wr-flit ×N flit_wr +C rd-flit ×N flit_rd ) / T

[0066] In the formula, C rd-flit is the average power consumption coefficient of the router to read a single data slice operation, C wr-flit is the average power consumption coefficient of the router writing a single data slice operation.

[0067] The hardware implementation of the simplified power consumption model is shown in Figure 6. It is mainly composed of 10 MUX, 10 AND gates, 4 adders, 1 divider and 1 m-order shift register. The biggest difference from the complete model is that the simplified model only uses one-of-two MUX, AND gate and adder to realize the statistics of read and write operation power consumption, eliminating the need for complex units such as S statistic and multiplier, greatly reducing ...

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Abstract

The invention discloses a router power model on the basis of a network-on-chip, which simplifies router operations into four power dissipation links namely write-cache, read-cache, a bestride switch and a bestride link according to the power dissipation specific weight and attributes dynamic power dissipation to bit flipping activities which are triggered when a present data film arrives, and numbers the power dissipation by the bit flipping activities to obtain the router power model. Considering that the implementation complexity which is required by the network-on-chip requirements to the power model is as low as possible, the invention can adopt the statistical average in stead of the instantaneous sampled value to obtain a power dissipation simplified model. Hardware implementation methods of two power dissipation models are given out aiming at a five-channel rooter structure, the simplified model is introduced to a self-adaptive routing algorithm, which realizes the power dissipation distribution optimization of the network-on-chip. The router power model which is proposed by the invention has low algorithm complexity and simple realization, is suitable for network-on-chip, and can be used in research and application in the aspects of power dissipation performance statistics, the power dissipation distribution optimization, thermal protection and the like.

Description

technical field [0001] The invention relates to a router power consumption model applied to an on-chip network, in particular to a low-complexity router power consumption model based on an on-chip network. Background technique [0002] Network-on-chip (NoC) provides a new paradigm for future complex System on a chip (SoC), and has recently received increasing attention. When the scale of NoC's on-chip integration becomes larger and larger, the power consumption of the network becomes one of the key design issues, such as power distribution optimization and thermal protection. [0003] Network-on-chip router power consumption model The main task of the power consumption model is to count the power consumption status of the router in real time, so as to support power management functions such as power consumption performance statistics, power consumption distribution optimization, and thermal protection of the network-on-chip network. The trade-off factors of the power consum...

Claims

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Application Information

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IPC IPC(8): H04L12/02H04L12/56H04L45/60
Inventor 李丽杨盛光张宇昂高明伦李伟何书专
Owner NANJING UNIV
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