Method for reducing dynamic power dissipation and electronic device

Abstract

The present invention relates to a method for reducing a dynamic power dissipation and an electronic device. The method is used to reduce the dynamic power dissipation of a slave unit, and comprises the steps of receiving a bus signal when access information of the slave unit is existed in the bus signal; inputting a clock signal to the slave unit and detecting a state signal sent by the slave unit; when the state signal of the slave unit displays that the slave unit is located in a free state, stopping inputting the clock signal to the slave unit. In the invention, by controlling work clocks of chip inner device modules, such as the slave unit, etc. via the bus signal and the slave unit, the chip inner device module is avoided from generating an unnecessary circuit turnover under a non-work state, to thereby achieve the purpose of reducing the dynamic power dissipation of the chip inner device module.

Description

technical field [0001] The invention relates to an energy-saving technology of an equipment module in a chip, in particular to a method for reducing dynamic power consumption and electronic equipment. Background technique [0002] With the application and development of wireless chips, reducing chip power consumption has become an increasingly urgent requirement. [0003] Wherein, the power consumption of the chip includes static power consumption and dynamic power consumption. [0004] For example, the bus architecture based on AMBA2.0AHB includes three parts: bus (AHBLocalBus), master module and slave module. The master device module and the slave device module can be devices such as IP cores, chips, or functional modules, and are all connected to the AMBA bus. The dynamic power savings of the master and slave modules depends on the ability to shut down the internal logic of these devices when not in use. [0005] A method to reduce the power consumption of master-slave...

AI Technical Summary

Problems solved by technology

[0008] This method of reducing dynamic power consumption uses a synthesis tool to automatically enter and exit the gate control unit according to the logic function. In the actual implementation process, only a small part of the circuit in the chip or programmable device can be optimized for gate control, and there is no way for large logic The circuit is optimized for gating, so the overall gating effect is not obvious, and the power saving benefit is not obvious

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