Design method of low-power consumption high performance high speed scratch memory

A high-speed temporary storage and design method technology, which is applied in energy-saving computing, memory systems, instruments, etc., can solve the problems that software cannot control cache data replacement, increase high-speed buffer power consumption, and affect processor performance. System performance enhancement, size reduction, performance enhancement effects

Inactive Publication Date: 2008-05-14
ZHEJIANG UNIV +1
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  • Abstract
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  • Application Information

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Problems solved by technology

[0007] On the other hand, since the cache is transparent to the software, the software cannot control the data replacement of the cache
In some applications, due to the random replacement of data, the...

Method used

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  • Design method of low-power consumption high performance high speed scratch memory
  • Design method of low-power consumption high performance high speed scratch memory

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Embodiment Construction

[0033] In the present invention, the high-speed scratchpad is a storage area with continuous storage addresses located on the processor, and is a mapping of an effective part of the memory. Its position and function in the processor pipeline are shown in Figure 1.

[0034] By designing the access mechanism and physical structure of the high-speed register, the useless power consumption in the process of accessing the high-speed register is avoided, and by increasing the controllability of the data backfill strategy of the high-speed register, the processor system is improved. performance. Its overall architecture and working principle are shown in Figure 2.

[0035] The design method of a kind of low-power consumption high-performance high-speed register that the present invention proposes, its feature comprises as follows:

[0036] 1) The high-speed scratchpad supports two modes of high buffering and local storage;

[0037] 2) The high-speed scratchpad supports dynamic swi...

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Abstract

The invention discloses a design method of a high speed register with low power consumption and high capacity. On the one hand, the invention prevents the invalid visiting to the high speed register by beforehand obtaining the information whether the high speed register is hitting and reduce the dynamic power consumption; on the other hand, the invention divides the storing district in to a number of physical blocks and only visit 1/n of the total size under the hitting status of the high speed working-storage section, the dynamic power consumption is 1/n of the original situation. The invention saves the switching time of the dummy address to the physical address, reduces the extra hardware spending brought by the address switching and reduces the whole power consumption of the system byadopting the dummy address to search the high speed register. The invention can greatly reduce the power consumption of the high speed register and greatly elevate the whole capacity of the highly embedding type processor being utilized, which has the advantages of low hardware cost and simple design realization.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a design method of a high-speed register with low power consumption and high performance. Background technique [0002] Embedded systems have penetrated into every aspect of daily life. Embedded systems are found in cell phones, portable multimedia players, digital cameras, and set-top boxes. The continuous expansion of the embedded field and the continuous complexity of the application have put forward higher requirements for the performance and power consumption of the embedded processor. [0003] Since the instructions and data required by the embedded processor are stored in the memory, it takes a lot of time for the processor to access the memory each time, which causes a serious pause in the pipeline and has a huge impact on the performance of the processor. The mismatch between processor speed and memory speed has become a huge obstacle limiting the performance o...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F13/28G06F1/32G06F12/0877
CPCY02B60/1225Y02B60/1235Y02B60/1228Y02D10/00
Inventor 严晓浪陈志坚孟建熠葛海通
Owner ZHEJIANG UNIV
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