The invention discloses a low-power, low-area, non-compete 1 bit full adder standard cell, having first to third input terminals, a Carry bit output terminal and an And bit output terminal, wherein the minimum operating voltage is less than or equal to 0.81V, the low-power, low-area, non-compete 1 bit full adder standard cell comprises: an exclusive OR circuit, for generating an exclusive OR signal required by And bit and Carry bit output; a summing circuit for outputting an And bit related signal; and a Carry bit output circuit, which outputs Carry bit result using coupling of a transmission pipe to a mirror circuit. The working condition of the circuit of the invention covers all process corners and harsh temperature ranges (-40 DEG C to 125 DEG C), there is no competition of Carry bit output terminal, and the invention is applicable for computing cell modules in various consumer electronic products.