Wafer-level electric leakage reducing ESD structure

Abstract

The invention discloses a wafer-level electric leakage reducing ESD (Electro-Static Discharge) structure, which comprises a control circuit, a feedback circuit, a bleeder circuit and a clamping circuit which are packaged by adopting a wafer-level packaging process, wherein the first input end of the control circuit is connected with a power supply VCC1, the second input end of the control circuit is connected with a power supply VCC2, the first output end of the control circuit is sequentially connected with the feedback circuit, the bleeder circuit and the clamping circuit, and the second output end of the control circuit is connected with the feedback circuit; the output end of the feedback circuit is connected with the output end of the bleeder circuit; the output end of the bleeder circuit is connected with the first input end of the clamping circuit, and the second input end of the clamping circuit is connected with a power supply VDD. Through the control circuit, the feedback circuit, the bleeder circuit and the clamping circuit which are packaged by a wafer-level process, the occupied area of a chip can be effectively reduced, the stability of output voltage is improved, the safety and stability of the chip and the circuit after ESD (Electro-Static Discharge) occur are ensured, and meanwhile, the loss caused by electric leakage is reduced.

Description

technical field [0001] The present invention relates to the field of electrostatic protection circuits, in particular, to an ESD structure for reducing leakage current at the wafer level. Background technique [0002] Electrostatic discharge (ESD (Electro-Static discharge)) is a common phenomenon in nature. And static electricity is a deadly threat to integrated circuit chips. It can generate a large current in a short period of time and cause irreversible damage to integrated circuit chips. According to statistics, the economic loss caused by electrostatic discharge in the semiconductor manufacturing industry reaches billions of dollars every year. Therefore, ESD protection design has also become an indispensable link in integrated circuit design. However, there is also an irreconcilable contradiction between the anti-ESD capability of the integrated circuit chip itself and the development direction of the integrated circuit. The design purpose of the ESD protection circ...

AI Technical Summary

Problems solved by technology

[0004] In the prior art, for the leakage protection between the power supply of the transmitting end and the power supply of the receiving end, at present, the termination resistance and the current source are mainly closed. Even if the leakage path of the driver stage itself is turned off, due to the ESD on the IO interface Diode, when the power supply of the sending end drops to the conduction voltage of the diode, the ESD diode will still conduct, and there will still be a leakage path, which cannot completely cut off the leakage current path, resulting in unnecessary leakage power consumption and reducing the IO chip service life

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