A Low-power, low-area, non-compete 1 Bit full adder standard cell

Abstract

The invention discloses a low-power, low-area, non-compete 1 bit full adder standard cell, having first to third input terminals, a Carry bit output terminal and an And bit output terminal, wherein the minimum operating voltage is less than or equal to 0.81V, the low-power, low-area, non-compete 1 bit full adder standard cell comprises: an exclusive OR circuit, for generating an exclusive OR signal required by And bit and Carry bit output; a summing circuit for outputting an And bit related signal; and a Carry bit output circuit, which outputs Carry bit result using coupling of a transmission pipe to a mirror circuit. The working condition of the circuit of the invention covers all process corners and harsh temperature ranges (-40 DEG C to 125 DEG C), there is no competition of Carry bit output terminal, and the invention is applicable for computing cell modules in various consumer electronic products.

Description

technical field [0001] The invention relates to a basic circuit unit in the field of digital integrated circuits, in particular to a standard unit of a 1-bit full adder with low power consumption, low area and no competition, which can be used in the design of a standard unit library. Background technique [0002] The Graphic Processing Unit (GPU) is the most widely used processing unit in current multimedia application equipment. In the Graphic Processing Unit, due to the limited capacity of the battery, the Graphic Processing Unit in the system needs to have extremely low power consumption. To prolong life, these processors do not require high speed, so the low power consumption circuit we designed is used in processors that require low power consumption. [0003] The data path is the core of the processor. A typical data path is composed of an arithmetic operation unit and a logic operator. The adder is one of the most commonly used and core units on the data path. There...

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Problems solved by technology

[0011] In order to overcome the deficiencies in the above-mentioned prior art, the purpose of the present invention is to provide a low-power, low-area, non-competitive 1-bit full adder standard cell, which solves the full adder output signal competition in the existing standard cell library Problems and problems of high power consumption, realized a low power consumption, low area and non-competitive 1-bit CMOS full adder circuit that can be used in standard cell libraries and can work in various process angles, temperatures, and low supply voltage environments

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