Power consumption reduction method for intellectual core and functional module for chip system

A technology of intellectual property cores and functional modules, applied in the direction of data processing power supply, etc., can solve the problems of incomplete reduction of power consumption and error-prone, and achieve the effects of reducing jumps, reducing dynamic power consumption, and reducing leakage power consumption

Inactive Publication Date: 2008-12-10
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to overcome the incomplete and error-prone problems of reducing power consumption in the prior art, thereby providing an improved power consumption reduction method for IP cores and functional modules in SoC

Method used

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  • Power consumption reduction method for intellectual core and functional module for chip system
  • Power consumption reduction method for intellectual core and functional module for chip system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] Such as figure 1 As shown in , this embodiment is a schematic diagram of reducing power consumption of the original IP core described in an explicit state.

[0025] Step a) Divide all the states of the original IP core into two categories - "idle" state and "working" state, the "working" state is not the "idle" state, and the "idle" state means that the IP core is not currently working effectively status. details as follows:

[0026] Among the figure, the working model of the original IP core 10 is in the box, and the state of the original IP core 10 has "idle", "request", "ready", "running", "end"; when in the "idle" state, If the bus has no request, it remains in the "idle" state, and if the bus sends a request, it enters the "running" state; the circle in the figure indicates the state, and the arrow indicates the transition, indicating the next state of the state machine. The state in the actual circuit of the original IP core 10 is realized by a series of regist...

Embodiment 2

[0036] figure 2 It is a schematic diagram of reducing power consumption of the original IP core described in an implicit state according to another embodiment of the present invention, and illustrates a specific method for performing low-power transformation. The original design pipeline of this IP core is divided into three pipelines, and each level is a register slot containing many register bits. The method for reducing power consumption in this embodiment includes:

[0037] Step a) Divide all the states of the original IP core into two categories - "idle" state and "working" state, the "working" state is not the "idle" state, and the "idle" state means that the IP core is not currently working effectively status.

[0038] The original IP core of this embodiment is different from most IP cores in that there is no explicit state machine description in the design code described by the hardware description language, and its state is implicitly represented by the effective b...

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Abstract

The invention discloses a power decreasing method of various intellective property core and functional module in SoC, which comprises the following steps: a) dividing all states of original functional module to two specie-' free' state and ' working' state; b) providing a logic circuit; connecting to the original functional module; constructing new low power functional module; finishing the logic function with the logic circuit; keeping clock close if without request for the original functional module; opening the clock if with the request for the original functional module; entering the original functional module into the ' working' state; closing the clock till the original functional module in ' free' state without bus request. This invention decreases dynamic state and leaking power consumption of IP core and auto-switches power source of the IP core at the same time.

Description

technical field [0001] The present invention relates to microprocessor architecture and integrated circuit technology, in particular to a method for reducing power consumption of various Intellectual Property (Intellectual Property, hereinafter referred to as IP) cores and functional modules in a System-on-Chip (hereinafter referred to as SoC) . Background technique [0002] As we all know, the key to improving the efficiency of SoC design depends on the reusability of IP cores. The IP core is the refinement of engineers' research and design. It mainly realizes some common functions that are difficult to design. These IP cores are generally verified, so that SoC designers can directly use these IP cores without repeating the design, thereby shortening the time design cycle and improve system reliability. Therefore, the IP core is the basic unit of SoC, and to reduce the power consumption of SoC, it is necessary to design a low-power IP core. [0003] There are two existin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/32
Inventor 常晓涛张明明艾霞张志敏
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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