Circuit and control method for reducing leakage current of sram storage array

Abstract

The invention discloses a circuit and a control method for reducing the leakage current of an SRAM storage array, comprising a storage array power supply voltage control module, a storage array ground terminal voltage control module and a storage array; The terminal control module realizes the control of the voltage of the power supply terminal and the ground terminal of the storage array, which can reduce the actual data retention voltage of the storage unit, thereby reducing the leakage power consumption of the SRAM in the data retention state. And the function of adjusting the data retention voltage value of the memory cell is realized by controlling different adjustment signals to meet different design requirements. The invention can effectively reduce the leakage current of the storage array in the data retention state of the SRAM, and in the storage system realized by the SRAM, the necessary SRAM can keep the data with low leakage overhead, and the other SRAMs can completely turn off the power.

Description

technical field [0001] The invention belongs to the technical field of SRAM, and in particular relates to a circuit and a control method for reducing the leakage current of an SRAM memory array. Background technique [0002] With the continuous development of IoT technology, the demand for energy-efficient microcontrollers for IoT sensor nodes is growing rapidly. Due to the battery-powered characteristics, the low-power design of microcontrollers becomes the key. The typical working characteristic of microcontrollers used in IoT technology is that they stay in sleep mode for a long time. Therefore, it is particularly important to reduce the leakage power consumption of microcontrollers in sleep mode. The static leakage power consumption of SRAM is the main source of power consumption. [0003] In the prior art, the peripheral logic circuit of the SRAM in the sleep state usually uses power gating to reduce leakage current, and the storage array only limits the leakage power c...

AI Technical Summary

Problems solved by technology

[0003] In the prior art, the peripheral logic circuits of SRAM usually use power gating to reduce the leakage current in the sleep state, and the storage array only limits the leakage power consumption by turning off the power gating when the data does not need to be kept.

For some SRAMs that need to save data, the storage array is still in the normal power supply state, resulting in a large leakage power consumption of the storage array, which limits the further improvement of the energy efficiency of the microcontroller