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Power gating method and device

A technology of power gating and power enabling, which is applied in the field of integrated circuits, can solve the problems of wasting power consumption optimization space, memory access modules cannot accurately use traditional power gating methods, etc., and achieve the effect of reducing leakage power consumption

Active Publication Date: 2017-05-24
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a power gating method and device, which are used to solve the problem that the traditional power gating method cannot be accurately used when the memory access module is working, thus wasting potential power consumption optimization space

Method used

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  • Power gating method and device

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Experimental program
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Embodiment 1

[0019] Such as figure 1 As shown, it is a schematic flow chart of Embodiment 1 of the power gating method provided by the present invention, which specifically includes the following steps:

[0020] S101. Generate a power-on enable signal, and the power-on enable signal is generated according to the opening time of the memory access window allocated for the memory access module;

[0021] Preferably, the power-on enable signal can be generated according to a preset time before the opening time of the memory access window assigned to the memory access module.

[0022] Specifically, the power-on enable signal in this embodiment can be executed by the scheduling module in the power gating device of the present invention, wherein the scheduling module can be implemented by a memory access scheduler, and the memory access scheduler can A memory access window is allocated to the memory access module, so that the memory access module sends the memory access requests intensively withi...

Embodiment 3

[0035] Such as image 3 As shown, it is a schematic structural diagram of an embodiment of a power gating device provided by the present invention, specifically including:

[0036] The scheduling module 31 is configured to generate a power-on enable signal, and the power-on enable signal is generated according to the opening time of the memory access window allocated for the memory access module;

[0037] Wherein, the scheduling module 31 may be a memory access scheduler in the prior art.

[0038] The power gating module 32 is configured to power on the memory access module according to the power-on enable signal generated by the scheduling module.

[0039] Further, the scheduling module 31 is further configured to: generate a power-off enable signal according to the time when the memory access result is returned to the memory access module;

[0040] Correspondingly,

[0041] The power gating module 32 is configured to: power off the memory access module according to the po...

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Abstract

The invention discloses a power supply gating method and device. The method includes the steps that a power-on enable signal is generated according to the opening time of a memory accessing window distributed to a memory accessing module; the memory accessing module is powered on according to the power-on enable signal. Because the power-on enable signal is generated according to the opening time of the memory accessing window distributed to the memory accessing module and the memory accessing module is powered on according to the power-on enable signal, the memory accessing module is in a working state only in the memory accessing window, and accordingly scattered time consumed in memory accessing delay and memory accessing conflict, idle time and the like are integrated into a long idle time period; by adopting power supply gating in the memory accessing module, the memory accessing module is in a power-on state only in the memory accessing window, and accordingly the leakage power of the memory accessing module is greatly reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a power gating method and device. Background technique [0002] With the continuous improvement of technology and the continuous improvement of circuit integration, leakage power consumption has become an important part of the overall power consumption of the chip. At 32nm and 22nm process nodes, leakage power consumption ranges from 16.9% to 52.7% of total power consumption. Therefore, more and more energy will turn to the research of leakage power consumption. [0003] Among them, power gating is a widely used technique for reducing leakage power consumption, that is, a power switch is added between a circuit module and a power supply (power supply and / or ground) to realize gate control of a corresponding circuit. The traditional power gating method is to turn off the power of a circuit module through a power switch when it is not needed, and almost all leakage po...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/32
Inventor 刘苏苏孟豪姜文奇
Owner LOONGSON TECH CORP
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