A Parallelism Adjustment Algorithm to Reduce Power Consumption of Instruction-Level Parallel Processors

Abstract

The invention relates to a parallelism degree adjustment algorithm for reducing power consumption of an instruction-level parallelism (ILP) processor. The algorithm comprises the steps of analyzing hardware resources and parallelism degree demand quantity information of parts of an input application program by utilizing a compiler, and obtaining a control flow graph (CFG) and loop hierarchy trees (LHTs) of the application program; dividing the application program: cutting the application program into different regions; setting executive parallelism degrees of the regions according to the hardware resources, the parallelism degree demand quantities and energy efficiency of the regions, so that the parallelism degree can be adjusted and changed according to the demands of executive time in the whole program execution process; and re-scheduling the program by the compiler, scheduling the regions by using the set parallelism degrees, inserting a power gating instruction before the regions are executed, and turning off idle hardware resources to reduce electric leakage power consumption. According to the algorithm, the influence of electric leakage power consumption on working performance of the processor can be reduced and the utilization rate of the hardware resources in the ILP processor can be increased.

Description

[0001] Technical field [0002] The invention belongs to the technical field of computer architecture design and relates to a low power consumption design optimization algorithm. Background technique [0003] In recent years, electronic products such as smartphones and wearable smart devices have developed rapidly, and almost everyone owns an electronic device. Although the emergence of these electronic devices facilitates people's lives, the execution speed can meet the needs of most users , but the power consumption problem is particularly prominent, which often affects the performance, reliability and operation time of the equipment; especially in the Internet + era, the performance requirements for computers and smart machines are getting higher and higher, and it is more and more important to improve the energy efficiency of equipment Practical significance. [0004] The main reason for the fast execution speed of these electronic devices is the application of an instruc...

AI Technical Summary

Problems solved by technology

However, the current research is only limited to the premise that the entire program is executed at the fastest speed, and those idle devices are turned off to reduce leakage power consumption. Sometimes users do not have such high expectations for speed, but power consumption is a problem. It attracts their attention even more, so it is of great practical significance to design an algorithm that can "automatically" adjust the parallelism of program execution according to the user's requirements for execution time, thereby reducing power consumption.

[0006] The AFReP algorithm proposed by Tabkhi in 2014 only inserts powergating instructions before executing each function in the application program, which leads to frequent opening of hardware devices, that is, changing the hardware configuration every time a function is entered, and frequent opening of hardware devices leads to A large amount of additional energy consumption is generated, and the overall evaluation of the energy-saving effect of AFReP, although the leakage energy consumption is reduced, but it produces a large amount of additional energy consumption, the effect is not good; and the AFReP algorithm can only reduce the power consumption when the execution speed is the fastest. consumption, and the degree of parallelism cannot be adjusted according to the user's needs to achieve an "automatic" effect, which is a defect of the algorithm

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