Low-electric-leakage bi-CPU core safe chip configuration

Abstract

The invention provides a low-electric-leakage bi-CPU core safe chip configuration, which realizes minimal safe physical isolation and static power consumption. The configuration employs two CPU subsystems, one of which is a low performance and low power dissipation logic gate count for processing communication interface and other non-security applications. The other CPU subsystem is a high-performance high-security CPU for providing complex and high performance cipher calculation, sensitive information processing and other high security applications. The high-performance CPU system is high in logic complexity, and a power supply is cut off by a gate control when a chip enters into a standby state to lower the integral electric leakage and power consumption of the chip.

Description

technical field [0001] The invention proposes a security chip architecture and design method capable of maintaining low leakage in the Standby state, which is applicable to the field of security chip design. Background technique [0002] The power consumption of CMOS integrated circuits includes dynamic power consumption and static power consumption. The dynamic power consumption is caused by the charging and discharging of the load capacitance by the power supply after the N tube or P tube is turned on. Static power consumption, also known as leakage power consumption, is the leakage power consumption generated by the power supply through the closed N tube or P tube to the ground. Before the chip processing technology entered the deep submicron process, the dynamic power consumption of the chip accounted for the main part of the overall power consumption of the chip. The proportion gradually increased. According to statistics, in the 90nm process, if the dynamic power con...

AI Technical Summary

Problems solved by technology

When the security chip processing technology level is 90nm, static power consumption has not yet become an obstacle to low-power chip applications

At present, the security chip processing technology is migrating to 65nm, 55nm or even 40nm, the static power consumption cannot be ignored, and a new design method is needed to ensure the power consumption level of the security chip in the Standby state

In addition, safety applications and non-safety applications are completed by a separate CPU, which requires additional safety isolation design for the software system to ensure the overall security of the chip, which increases the difficulty of software design

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