Low-electric-leakage bi-CPU core safe chip configuration

A security chip, nuclear security technology, applied in data processing power supply, electrical digital data processing, instruments and other directions, can solve the problems of static power consumption can not be ignored, software design increases the difficulty, etc., to achieve the effect of reducing the overall power consumption

Inactive Publication Date: 2016-11-02
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Abstract
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Problems solved by technology

When the security chip processing technology level is 90nm, static power consumption has not yet become an obstacle to low-power chip applications
At present, the security chip processing technology is migrating to 65nm, 55nm or even 40nm, the static power consumption cannot be ignored, and a new design method is needed to ensure

Method used

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  • Low-electric-leakage bi-CPU core safe chip configuration
  • Low-electric-leakage bi-CPU core safe chip configuration

Examples

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[0009] As shown in Figure 2, in the security chip, there are two CPU subsystems, one is the CPU_1 subsystem (200) and the other is the CPU_2 subsystem (300). The CPU_1 subsystem completes communication interface processing and instruction analysis, and the CPU_2 subsystem provides cryptographic computing services and sensitive information processing. The CPU_1 subsystem and the CPU_2 subsystem have their own physically separated memory resources, and exchange data through a dedicated data channel (270).

[0010] CPU_1 (222) can use standard 8051 low logic gates and low computing power non-safe CPU core, in order to achieve communication processing and instruction analysis, through a simple system bus integrated memory unit_1 (221), communication interface unit (223) And the system control unit (224), the memory unit_1 includes RAM and ROM required for the normal operation of CPU_1. Due to its simpler functions, the size of this part of the memory is much lower than that of the C...

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Abstract

The invention provides a low-electric-leakage bi-CPU core safe chip configuration, which realizes minimal safe physical isolation and static power consumption. The configuration employs two CPU subsystems, one of which is a low performance and low power dissipation logic gate count for processing communication interface and other non-security applications. The other CPU subsystem is a high-performance high-security CPU for providing complex and high performance cipher calculation, sensitive information processing and other high security applications. The high-performance CPU system is high in logic complexity, and a power supply is cut off by a gate control when a chip enters into a standby state to lower the integral electric leakage and power consumption of the chip.

Description

technical field [0001] The invention proposes a security chip architecture and design method capable of maintaining low leakage in the Standby state, which is applicable to the field of security chip design. Background technique [0002] The power consumption of CMOS integrated circuits includes dynamic power consumption and static power consumption. The dynamic power consumption is caused by the charging and discharging of the load capacitance by the power supply after the N tube or P tube is turned on. Static power consumption, also known as leakage power consumption, is the leakage power consumption generated by the power supply through the closed N tube or P tube to the ground. Before the chip processing technology entered the deep submicron process, the dynamic power consumption of the chip accounted for the main part of the overall power consumption of the chip. The proportion gradually increased. According to statistics, in the 90nm process, if the dynamic power con...

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Application Information

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IPC IPC(8): G06F21/76G06F1/32
CPCG06F21/76G06F1/3243
Inventor 陈波涛范长永关红波蒙卡娜于敦山
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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