124 results about "Logic complexity" patented technology

The invention discloses an acceleration method for realizing sparse convolutional neural network inference for hardware. The method comprises a grouping pruning parameter determination method facing asparse hardware acceleration architecture, a grouping pruning training method for sparse hardware acceleration architecture and a deployment method for forward inference of a sparse convolutional neural network. determining the packet length and the pruning rate of packet pruning according to the number of multipliers in the hardware architecture; based on the magnitude cutting mode, cutting weights except the compression rate; The network accuracy and compression rate after pruning are improved through an incremental training mode, the weight and index parameters of a non-pruning position are saved after the pruned network is finely adjusted, the network is sent to a computing unit under a hardware architecture, and the computing unit obtains the activation value of the packet length atthe same time to complete sparse network forward inference. The pruning parameters and the pruning strategy of the algorithm level are set based on the hardware architecture, the logic complexity of the sparse accelerator is reduced, and the overall efficiency of forward inference of the sparse accelerator is improved.

The invention relates to a floating point addition device based on complement rounding, which supports the floating point addition operation and the floating point subtraction operation. The floatingpoint addition device comprises an exponent adder, a mantissa shifter, a mantissa operand preparation logic unit, a mantissa adder, a rounding judgment logic unit and a rounding adder, wherein the mantissa operand preparation logic unit is used for processing the mantissa operand according to sign bits and the exponent difference of the first floating point operand and the second floating point operand, the rounding judgment logic unit is used for executing the uniform rounding judgment on a mantissa addition result, judging the positive and the negative of the mantissa sum according to the highest bit output by the mantissa adder, determining a constant bit for the rounding judgment according to the highest four bits output by the mantissa adder, and unifying original code rounding plus 1judgment logic and complement rounding plus 0 judgment logic; and the rounding adder is used for rounding the mantissa addition result of the floating point and finishing the code extraction and complement operation to the mantissa sum. The invention has the uniform mechanism, avoids the special complex mantissa operand preparation and rounding judgment logic of the floating point addition, and reduces the logic complexity.

The invention discloses a delta-sigma modulator based on the digital-noise coupling technology. The structure of a traditional noise coupling delta-sigma modulator is improved, and the output of a quantizer is divided into an MSB part and an LSB part. The MSB part is directly fed back to the input end of the modulator; the LSB part is fed back to the input of the quantizer after digital-to-analogue conversion; then the MSB part and the LSB part are recombined after digital post-processing. The digital-noise coupling technology can fully represent the performance advantage of the high-precision quantizer, the problem of the exponential growth of the matching logic complexity of dynamic components is avoided, the logic time delay of introduction of a digital delta-sigma remodulation scheme provided by formers is also avoided, the quantizing noise leakage caused by mismachining between analog and digital noise transfer functions is further restrained, and therefore the requirement for design of an operational amplifier is lowered, implementation is easy, and the modulator is very suitable for low-power dissipation and broadband application.

The invention discloses a TD-SCDMA uplink transmission channel processing method. By the method, the processing of each 10 ms of each transmission channel is successively finished, and ordering processing of the TTIs of eight transmission channels according to size is unnecessary, so that the processing logic complexity is reduced. By using the method, it is unnecessary to store data of all the transmission channels in a large memory to select the 10 ms for processing, instead, data of one 10 ms currently to be processed is directly stored only, and data selection is finished by use of a memory, such that the realization is visual and convenient, the logic processing difficulty in determining a data storage position is reduced, the requirement for interlacing the storage space of the memory at a time is reduced, and the effect of optimizing a whole uplink area is achieved.

The invention discloses an online BIOS (basic input/output system) refreshing method for a multi-node server. The method comprises steps as follows: a two-stage gating switch circuit comprising a first-stage gating switch and second-stage gating switches is arranged between a BMC (baseboard management controller) and CPU (central processing unit) nodes, after initialization of the BMC is completed, a driver of an SPI (serial peripheral interface) controller is uploaded, an online BIOS refreshing command on a user side is waited, when the online BIOS refreshing command is received, target CPU nodes are determined, the two-stage gating switch circuit is set for gating of BIOS Flash of the target CPU nodes, a BIOS updating file is obtained from the user side, the BIOS updating file is executed for updating, and the state of the two-stage gating switch circuit is restored. With the adoption of the method, the problem about BIOS refreshing of high-density server nodes can be effectively solved, CPUs on a main board can be updated without electrification, the single BMC can manage BIOS refreshing of the multiple CPU nodes, and the method has the advantages that remote operation is realized, the method is simple and convenient, the hardware logic complexity is low, embedded software is simple to realize, the method is convenient to use and the user experience is good.

The invention provides a solid-state disk (SSD) storage device and a data access method of the SSD storage device. The problems existing in the prior art that the data management of an SDD is high in complexity, and NandFlash physical pages in a NandFlash physical block are inconsistent in the service life are solved. According to the invention, the user data area, first order metadata and the length of an ECC in each storage cell of the SSD storage device are set to be fixed values, the format of data stored in each storage cell is fixed, the ECC can guarantee the consistency of data in the user data area and the first order metadata according to a fixed code rate, the correctness and integrity of the data in the user data area and the first order metadata are guaranteed, data management is simplified, and the ECC hardware logic complexity is reduced; at the same time, because the ECC code rate is consistent, the consistency of the service life of each storage cell is guaranteed.

The application provides a test method and device under multi-environment; the method comprises the following steps: obtaining user set environment parameters and pre-configured common data, wherein the environment parameters comprise at least one environment label and environment configure data respectively corresponding to the at least one environment label, and the common data refers to the common data in the multi-environment; generating and executing corresponding test scripts respectively aiming at each of the at least one environment label according to the environment parameters and the common data. The method and device can test same test scene under various test environments, thus preventing logic complexity, reducing debug cost, preventing data error in execution, and realizing test script uniqueness under the specific test environment.

The invention provides a performance testing method of a simulation engine and a storage medium, and is applied to simulation of parallel discrete events. The method performance testing method of the simulation engine includes the steps of establishing and generating a simulation model, using information needed by application managing for configuring the simulation model, using synchronous-event scheduling performance, random-event scheduling performance, event queue managing performance and time marching efficiency to test the simulation model, according to selected performance indexes, preparing simulation event queues separately, and according to the selected performance indexes, starting simulation to start testing till treatment is completed or timing is completed. According to the performance testing method of the simulation engine, a parallel mode and a serial mode are compatible and can be switched; model logic participating in performance testing is extremely low in complexity, and the influence of simulation-model performance on engine performance testing is excluded; testing indexes mainly aims at time coordination of simulation engine event scheduling, can represent basic performance of the engine and has objectivity. An index testing method can be implemented on different simulation engines and has implementation feasibility.

The invention discloses a reusable pixel processing method and a reusable video processing chip. According to the method, a same pixel processing device is used for executing at least two types of pixel processing. The method includes: determining processing types for processing a current frame; configuring corresponding commands of the processing types in the pixel processing device; and performing processing of each execution cycle for to-be-coded macro blocks of the current frame sequentially by the aid of the configured commands corresponding to the determined processing types of the current frame. The video processing chip comprises a determining unit, an acquisition unit, a register array, a clock control unit, a controller and an arithmetic unit array. The reusable pixel processing method and the reusable video processing chip have the advantages that by the reusable design technology, registers and arithmetic units are configured by different methods, so that single hardware unit can be reused for multiple operations in a time division manner, computing and storage logic complexity of the chip is lowered, and the area and power consumption of the chip are reduced.

The invention relates to a rounding method for indivisible floating point division radication. The rounding method comprises the following steps: (1) executing an SRT division/radication algorithm toa floating point number input to a floating point coprocessor, and executing a loop operation to the floating point number and then obtaining a quotient/root result; (2) determining the effective number of the floating point number according to the appearance position of the first 1; (3) reducing the effective number result and a remainder obtained by the SRT division/radication algorithm from thequotient/root result of the step (1), and taking the difference as rounding judging information; and executing the left shift operation to the difference obtained by reducing the effective number result of the step (2) from the quotient/root of the step (1), and then taking the obtained number as a residue place; (4)-(7) selecting four kinds of different rounding modes to round; (8) if the rounding operation executed in step (4) to (7) causes the quotient/root result to have a carry bit or a borrow bit, modifying the floating point exponent part, wherein the final rounding result needs to execute the mantissa normalization. The rounding method can reduce the logic complexity, reduce the same hardware cost, and shorten the time sequence.

The invention provides a game verification method and device, a game server, a verification server and a game system. The method includes the steps that an operation sequence sent by a client when a game is operated at a client is received; the received operation sequence is sent to the verification server and used for the verification server to verify the game operated by the client according to the operation sequence; a verification result fed back by the verification server is received. By means of the game verification method and device, the game server, the verification server and the game system, the problems that in the prior art, when a game server is used for verifying a game of a client, computation cost of the game server is increased, and logic complexity of the game server is increased are solved, and the effect of greatly reducing loads of the game server is achieved.

The invention discloses a streaming media playback method. The streaming media playback method comprises the steps that an information forwarding module receives a streaming media playback instructionsent by a client; an application processing module receives the streaming media playback instruction, authenticates the legality of the streaming media playback instruction and outputs the legal streaming media playback instruction; and multiple service processing modules receive the legal streaming media playback instruction and look up related information of streaming media files requesting forplayback in a database, return streaming media playback addresses when the related information of the streaming media files exist in the database to enable the client to form a playback page, extracts corresponding storage addresses of the streaming media files from the database and return the storage addresses to the client to enable the client to acquire the streaming media files and load the streaming media files to the playback page. According to the method, the playback logic complexity of multiple streaming media files is reduced, the blocking and error problems of the playback page arereduced, the response speed of the streaming media playback page is increased, and the interaction experience of the streaming media playback page is improved.

The invention discloses an implementation method of a light embedded file system. The method includes the following steps that memory space of a device is divided into different types of clusters, theclusters include catalog entry clusters and file content clusters, the catalog entry clusters are used for storing index information of files or catalogs, and the file content clusters are used for storing file data. When the system is electrified, a cluster identifier of each cluster is scanned and cached, the types of the clusters are judged by reading the cluster identifiers, whether cluster content is legal or not is judged, and the power-on process is completed. The file system adopts a metadata scattered storage method, the requirement for the RAM capacity of the system is reduced, a file index value scattered storage mode is used for replacing a traditional chain table file maintenance mode, the logic complexity is low and the file access efficiency is high.

The embodiment of the invention provides a message monitoring method and device applied to host objects, used for generating a monitoring instance of a preset monitoring class, wherein the preset monitoring class is a subclass of a broadcast receiver class of the system; wherein the preset monitoring class is used for detecting a target broadcast message triggered when the Home key is clicked, thepreset monitoring class realizes reference to a host object through a preset monitoring callback interface, and registration is performed on a monitoring instance according to a registration method of the preset monitoring class so as to start monitoring the target broadcast message. Processing based on the above, the host object can interact with a preset monitoring class through a preset monitoring callback interface; according to the embodiment of the invention, the monitoring of the target broadcast message is realized according to the preset monitoring class, that is, the monitoring processing of the target broadcast message does not need to be completed in the host object, so that the logic complexity and the coupling degree of codes in the host object can be reduced, and the maintenance cost of the system is reduced.

The invention discloses a data redundant backup method, a data redundant backup system and a storage node server based on cloud storage. The method comprises the following steps: carrying out monitoring on a write operation command by the redundant driving unit of the storage node server; capturing the write operation command of writing data in main equipment by the redundant driving unit, and obtaining the global unique identification (GUID) of the main equipment; finding out corresponding redundant equipment GUID in the mapping relationship according to the main equipment GUID by the redundant driving unit; determining redundant equipment corresponding to the redundant equipment GUID to be online by the redundant driving unit, and writing data written into the main equipment in the redundant equipment. The scheme can realize real-time and quick redundant backup, and avoids logic complexity in the realization by adopting upper application.

The invention provides a cross-board processing method, apparatus and system of service messages. A main control board is connected with one or more service line cards; the main control board is provided with multiple virtual service ports, which are in one-to-one correspondence with the physical service ports of the service line cards and share the same port index; service messages sent by the service line cards are received by corresponding virtual service ports; forwarding query processing is performed on the service messages to obtain the port indexes of the virtual service ports corresponding to the destination addresses of the service messages; and the service messages are sent to the corresponding service line cards according to the port indexes corresponding to the destination addresses, so that the service line cards send the service messages through the physical service ports corresponding to the virtual service ports. By adoption of the cross-board processing method, apparatus and system, the logic complexity of the main control board software module and the coupling of the software modules of the main control board and the service line cards are reduced, and the robustness of the whole system is improved.

The invention belongs to the field of computer software, and provides a method and a device for complex time sequence processing queue dynamic prediction. The method comprises that all order operations are respectively and correspondingly divided into one or a plurality of atomic operations in advance; an order operation executing instruction is received, the corresponding atomic operations executing the order operations are added into a queue; and the atomic operations in the queue are carried out in sequence. According to the method and the device, logic complexity caused when the order operations are carried out is greatly simplified, and generating rate of BUG is reduced.

The invention discloses a multi-thread arithmetic coding circuit and method based on the standard JPEG 2000 and mainly aims to solve the problem of large area, low encoding efficiency and low throughput of a conventional multi-context arithmetic coder. The coding circuit is characterized in that under the premise of ensuring that the compression result is identical with that of the standard JPEG 2000, a command generating subunit, a command register and a comparator are introduced to a command generating and index forecasting unit' in the arithmetic coder, and the comparator is used for generating a 'command for controlling the thread coding mode; and simultaneously, an interval adjustment selector, a probability estimate selector and an index selector are controlled according to the command value to allocate the last coding result to the current to-be-coded thread, so that the logic complexity is reduced. Besides, according to the invention, LUTs (lookup tables) are split and expanded, wherein the primary LUT stores all possible index values, and the secondary LUT only stores probability estimate value. The simulation result shows that the invention has the characteristics of small area and high throughput and can be applied to high-performance image processing chips.

The invention discloses a method for performing communication among EDMA (enhanced direct memory access) different bandwidth devices in a multi-core DSP (digital signal processor). Each DSP core is provided with an independent processing channel, each channel is independent and can process requests from other DSP cores and other devices, a read operating information cache mechanism and a read operating information return data caching mechanism are realized through synchronous FIFO (first in, first out), accurate matching of return responding and requests is realized, and data communication among different bit width devices is realized. According to the method, read and write operation is controlled by state machines adopting the same working mechanism, and the logic complexity and the design difficulty are effectively reduced.

The invention discloses an identification method for a short message service (SMS) protocol and a gateway system. In the identification method, the gateway system receives a request message from a client by establishing a TCP (transmission control protocol) link, wherein the request message carries the IP (internet protocol) address message of the client; and the gateway system judges and determine the SMS protocol adopted by the TCP link based on the IP address message and the length information of the request message. By the technical scheme in the invention, the system configuration is simplified and the logic complexity of the system is reduced.

The invention discloses a data linking exception retry method based on a block chain. The method employs an independent scanning detection module, reduces the logic complexity and module responsibilities compared with a conventional mode of immediate retry when an exception occurs, and can prevent a part of data linking interruption and loss caused by service downtime in a conventional scheme. Through control via distributed locks, only one service in a plurality of levels of scanning detection services detects and scans records or data with data linking failure to determine whether to re-linkor not. The subsequent linking process is concurrently carried out through the linking service. so that repeated sending behaviors in a distributed lockless environment is avoided, and the overall efficiency and reliability of the linking process are improved.