17 results about "Logic complexity" patented technology

The invention relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata, and calculating to generate a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model, and outputting an initial adjacent matrix; calling a feedback suppression mask matrix generated based on a historical operator utility state, and executing bitwise logic AND operation with the initial adjacent matrix to generate a corrected effective topological matrix; the matrix is analyzed, a logic operator function pointer is dynamically indexed in an instruction cache, and a directed acyclic execution linked list is constructed; according to the method, redundant logic nodes in AI prediction are definitely eliminated through a bit operation mask mechanism based on historical feedback, and deterministic convergence of processing delay and optimal matching of computing power resources are achieved.

The application relates to a function module operation method, device and equipment and a storage medium, the method comprising the following steps: a first function module class corresponding to a first function module is created; the first function module class inherits a base class provided by a preset function module development framework; a data service interface for data interaction between modules and an execution interface for executing business logic in a module are arranged in the base class; first output data corresponding to a second function module relied on by the first function module is acquired through the data service interface in the first function module class; the first output data is data provided externally to the second function module through the data service interface in the base class; the execution interface in the first function module class is called, the first function module is operated based on the first output data according to preset business logic. The application reduces the complexity of control logic, reduces resource consumption and improves the decoupling degree between modules through a data driving mode.

The application belongs to the technical field of monotonic counter, and particularly relates to a monotonic counter, a counting method, an electronic device and a storage medium. The counting method of the monotonic counter of the application, under the condition that no abnormal situation occurs, only counts between two storage blocks in turn, and does not need to perform additional storage blocks to back up the storage block counting value under the abnormal situation, thereby optimizing the operation process of counting. Under the condition that an abnormal situation occurs, firstly, whether the external address is the start address of the data bit of the storage block is judged, and then whether the storage block has an abnormality is judged. For the storage block without an abnormality, the counting value is obtained by counting the data bit, so as to ensure accurate counting. For the storage block with an abnormality during counting, the storage block is switched to another storage block for erasing and then switched back to the current storage block for counting. The counting method optimizes the processing steps of counting and abnormal situations, and reduces the logic complexity.

The application relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata and calculating a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model to output an initial adjacency matrix; calling a feedback inhibition mask matrix generated based on a historical operator utility state, performing bitwise logical AND operation on the initial adjacency matrix to generate a corrected effective topological matrix; analyzing the matrix, dynamically indexing a logical operator function pointer in an instruction cache, and constructing a directed acyclic execution linked list; and driving a processor to sequentially call logical operator execution operation, wherein the application determines redundant logic nodes in AI prediction through a bitwise operation mask mechanism based on historical feedback, realizes the deterministic convergence of processing delay and the optimal matching of algorithm resource.

The application relates to a default value setting method, device, equipment, medium and program product of a nuclear power plant. The application relates to the technical field of nuclear power. The method comprises the following steps: acquiring an input signal of a function block in a digital control system of a nuclear power plant; determining a quality bit of the input signal according to a preset interval range and a numerical value in the input signal; and delivering the quality bit to other function blocks connected with the function block. The method can avoid increasing the logic complexity.

The present application relates to the technical field of chip design, in particular to a cross cache line data acquisition method, electronic equipment and storage medium, which obtains the maximum unit total amount M corresponding to the current subtask belonging to the graphics rendering command; reads and splices the data corresponding to the (M-1) subunits continuous at the end of the first cache line address range and the data corresponding to the (M-1) subunits continuous at the beginning of the second cache line address range, obtains the continuous data covering the complete access range of the current subtask and stores it in the preset buffer; according to the starting address of the current subtask and the first target number of the first target subunit falling in the first cache line, the target data is extracted from the buffer, and the target data is used as the input of the distribution operation, which reduces the logical complexity and the calculation complexity.

This utility model discloses a multi-system, multi-channel digital TR synchronization circuit, comprising a GPS / BD timing module, a system clock source, a multi-channel digital TR board, and a system lead generation device. The rubidium clock and second pulse of the GPS / BD timing module are respectively connected to the system clock source and the lead generation device. The sampling clock and lead clock of the system clock source, and the lead signal of the system lead generation device are respectively connected to each multi-channel digital TR board. The system lead clock of the system clock source is also connected to the lead generation device. This scheme uses the rubidium clock and second pulse of the GPS / BD timing module as a reference, and the accuracy of the lead clock determines the synchronization accuracy (e.g., a 20MHz lead clock synchronization error ≤50ns). Multi-system expansion can be achieved by adding timing modules without refactoring the hardware architecture. Its hardware and software integration reduces FPGA logic complexity, reduces hardware costs by relying on chip synchronization functions and equal-length wiring design, and ensures multi-channel synchronization stability through same-source clock allocation and equal-length signal design.

Provided in the present application is a PLC control system, comprising: a CPU module for executing application logic; a plurality of backplane modules connected in series and configured to connect the CPU module to functional modules, wherein each backplane module can be correspondingly connected to one functional module; and an artificial intelligence module, which is one of the functional modules, receives various data, performs data analysis processing on a data processing task of which the data volume exceeds a preset data volume threshold or the logic complexity exceeds a preset logic complexity threshold, and forwards obtained analysis data to the CPU module by means of the corresponding backplane module. The present application applies the edge computing concept to the field of PLCs, and migrates large-scale complex computing from the CPU module to the artificial intelligence module, thereby reducing the resource consumption of the CPU module, and improving the overall processing performance of the PLC control system. Large-scale complex computing is also usually prone to failure, such that individually performing large-scale complex computing by means of the artificial intelligence module also improves the reliability and availability of the CPU module.

The application relates to a simulation and calculation method for the coverage efficiency of a satellite networking area, and the method comprises the following steps: S100, editing and initializing a simulation scene; S200, parallelly simulating the space state of each satellite in the satellite networking through a plurality of simulation CPU threads, wherein the number of the satellite networking is one or more; S300, writing the data obtained after the editing and initializing of the simulation scene in step S100 and the space state data of each satellite obtained in step S200 into a GPU through at least one calculation CPU thread; and S400, parallelly calculating the coverage efficiency index of each satellite networking through the GPU. Through the heterogeneous multi-processor hybrid architecture of the multi-CPU and multi-GPU, the simulation part of the algorithm logic complexity but non-data intensive calculation is parallelly processed by the multi-CPU thread, and the simulation part of the algorithm logic simplicity but data intensive calculation is parallelly processed by the GPU, so that the calculation time is effectively reduced and the efficiency is effectively improved while the calculation precision is ensured.

The invention provides a natural language-oriented canvas generation method based on an intelligent canvas agent. The scheme comprises the following steps: acquiring an input natural language demand to obtain an input demand; performing intention analysis and command conversion on the input demand to obtain an execution command which is an instruction of a computer language; a canvas is generated according to the execution command, and the canvas is the canvas of the visual executable business strategy. According to the scheme, the problems that in the prior art, multi-channel service expansion logic is complex, A / B test configuration is wrong, and intelligent conflict detection and logic verification cannot be carried out are solved.

The embodiment of the invention provides a processor verification system and method, electronic equipment and a readable storage medium. The system comprises an equipment end and a processing end. The equipment end comprises at least two processor cores of a processor to be verified; the processing end comprises a network-on-chip, and the network-on-chip is used for data interaction among the processor cores in the equipment end; the equipment end is connected with the processing end through an optical module, and the optical module adopts a preset communication protocol. According to the invention, physical separation and logic centralized management are realized, and large-scale network-on-chip logic is stripped from a processor core end and centralized to a special processing end, so that the logic complexity of an equipment end where the processor core is located is greatly reduced.

The application discloses a software abnormal behavior early warning and intelligent tracing method and system for a secret-related environment, relates to the technical field of software development, and solves the technical problems that the abnormal escape rate is high, risk early warning lags behind, decision-making lacks basis, release management and control is extensive, tracing and positioning is inefficient, and it is difficult to adapt to the precise early warning and intelligent tracing demand of software abnormal behavior in the secret-related environment; the features extracted from the abstract syntax tree from the syntax level can get rid of the interference of the surface form of the code, accurately capture the structured nature of the secret-related code; the actual running path of the code is restored from the execution dimension through the control flow graph, and the quantifiable execution logic complexity is combined with the logic to enhance the features. The logic complexity analysis can quickly locate the high-risk features in the secret-related environment, and provide bottom feature support for the abnormal behavior early warning. The correlation analysis is based on the CFG and variable dependence; core quantitative indicators are set for each release link to realize link-level risk decomposition.

The invention provides a clock domain crossing counter device and a clock domain crossing method thereof, and the device comprises a low n-bit clock domain crossing processing module which processes low n-bit clock domain crossing processing of a counter; the high m-bit clock domain crossing control module is used for generating high m-bit clock domain crossing control logic according to values before and after low n-bit clock domain crossing of the counter; the high m-bit clock domain crossing processing module is used for finishing high m-bit clock domain crossing of the counter based on control logic driving of the high m-bit clock domain crossing control module; and high m-bit data sent by the counter accumulator is input into the first high m-bit register of the module. According to the scheme, a handshake type cross-clock domain is adopted, high logic complexity of a large-bit-width counter is avoided, time sequence performance is improved, register resource consumption is reduced, and the area is optimized.

The invention discloses a cross-terminal unified operation transmission system and method in a cloud game scene. The system comprises a client and a cloud game server; the client comprises a unified input capture module, an operation abstraction module, a coordinate scaling module and a binary coding module; the cloud game server comprises a binary decoding module, an event state management module, a coordinate restoration module and an event injection module. The method has the advantages that the operation delay is remarkably reduced, the data volume of a single operation message can be reduced by more than 75% by replacing JSON with a customized binary protocol, the network transmission time is shortened, the end-to-end operation delay is remarkably reduced, and the response speed and the hand feeling of the operation are greatly improved. Through operation abstraction and coordinate scaling of the client, the server does not need to perceive which equipment or input mode the front end is, all inputs are normalized, and logic complexity and code coupling degree of the server are greatly reduced.

The invention relates to the technical field of branch prediction circuits, in particular to an efficient and low-cost branch prediction circuit implementation method and system. Branch target information and a physical Tag value are extracted from an SRAM (Static Random Access Memory) with a multi-bank structure by taking a low-order part of a PC (Personal Computer) program counter as an index, and the Tag bit width is reduced by adopting a Hash compression mode, so that rapid fuzzy matching prediction is realized, and the comparison logic complexity and the storage occupation of the SRAM are remarkably reduced. A multi-bank interleaving storage structure is utilized, physical bank partitions of update writing and prediction reading are judged by accessing coding bits, parallel operation is achieved, the read-write conflict rate is reduced, and the continuity of instruction fetching flow is improved. Meanwhile, a renaming conflict detection and redirection mechanism is introduced in an instruction decoding stage, consistency verification is carried out on predicted and real branch types, and the correctness of instruction fetching is redirected. Under the condition of not reducing the prediction performance, the circuit working frequency is obviously improved, the chip area and power consumption are reduced, the implementation is simple, the cost is low, and the circuit performance can be obviously improved.

The invention relates to the technical field of in-memory calculation circuit design, and discloses a mantissa in-memory calculation unit based on 5-bit approximate square, a floating point in-memory calculation unit, a circuit and a chip. The mantissa in-storage calculation unit based on the five-bit approximate square comprises a full-precision mantissa adder, three five-bit square circuits and a multi-operand adder. According to the mantissa in-memory calculation unit based on the five-bit approximate square, mantissa multiplication is converted into a combination of square operation and additive operation, a five-bit square circuit is designed to carry out square operation on the high five bits of the mantissa, and a traditional multiplication function is achieved in an approximate mode; and the logic complexity and the hardware overhead are obviously reduced under the condition that enough precision is met. The problem that the precision and the energy efficiency of an existing mantissa multiplication circuit are not balanced is solved.

This application discloses a method, apparatus, computer device, and storage medium for determining a programming interface, relating to the field of software development. The method for determining the programming interface includes: parsing a production database to obtain attribute information for each service scenario; obtaining a rule base for the service scenario based on the attribute information; acquiring data information from the rule base and aggregating the data information to obtain an integrated data source; and determining the application programming interface based on the integrated data source and the rule base. By integrating the integrated data source and the rule base to obtain the application programming interface, a visual operation interface is provided for users, reducing the logical complexity of project development and testing. Simultaneously, a unified platform function is provided, simplifying the complexity of data generation from the data source and improving the efficiency of project development and testing.