52 results about "Logic complexity" patented technology

The invention relates to an automatic video editing method based on semantic analysis, and belongs to the technical field of video editing. The method comprises the following steps: extracting anchor point information of text content in a streaming media file based on a knowledge graph, establishing a support relationship, and determining a main anchor point, a sub anchor point and a argument anchor point by combining the support relationship and the anchor point information; constructing a dynamic trigger mechanism, setting a verification direction of the dynamic trigger mechanism, determining a semantic extension direction of the anchor point information according to the verification direction, and verifying whether a precondition chain supporting the anchor point information exists or not; and setting a credibility scoring strategy, determining the credibility of the anchor point information according to the logic complexity, the language confidence and the text consistency, forming a sequence set of the anchor point information, and splicing to form a logically coherent video editing text result. According to the method, automatic and intelligent editing of the video is realized based on semantic analysis, and the editing efficiency and quality are remarkably improved.

The invention relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata, and calculating to generate a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model, and outputting an initial adjacent matrix; calling a feedback suppression mask matrix generated based on a historical operator utility state, and executing bitwise logic AND operation with the initial adjacent matrix to generate a corrected effective topological matrix; the matrix is analyzed, a logic operator function pointer is dynamically indexed in an instruction cache, and a directed acyclic execution linked list is constructed; according to the method, redundant logic nodes in AI prediction are definitely eliminated through a bit operation mask mechanism based on historical feedback, and deterministic convergence of processing delay and optimal matching of computing power resources are achieved.

The invention discloses a cloud cipher machine cluster management method and device, and the device comprises a cloud cipher machine management platform, a cloud cipher machine host and a file server, does not depend on the equipment of a specific manufacturer, has certain universality, reduces the logic complexity of the cloud cipher machine management platform, improves the development and construction efficiency of a cipher management platform, and reduces the cost. Management of cloud password devices of different manufacturers is supported; the method comprises the following steps: receiving a cluster management request, and analyzing the cluster management request; analyzing the cluster management request, and calling a cluster management command line tool to complete cluster management work according to the cluster management instruction; obtaining a cluster node state according to the cluster state monitoring request, and calling a cluster monitoring command line tool according to the cluster monitoring instruction to obtain a current virtual machine state; and making a corresponding processing strategy according to the state of the virtual machine. Automatic drifting of fault nodes is supported, automatic fault repairing is achieved, fault time is shortened, operation and maintenance cost is reduced, and usability and reliability of a cloud cipher machine cluster are improved.

The embodiment of the invention discloses a communication method and device of a USB protocol, a storage medium and a USB host, and relates to the field of communication. According to the method, four basic endpoint queues (interrupt, synchronization, batch and control transmission queues) are initialized, and empty queue data are created for each queue, so that communication between the USB host and the USB slave is managed. When a pipeline creation or data transmission request of an application layer is received, the scheme can generate or update queue data and add the queue data into a corresponding queue. The queue data comprises key information such as a state flag bit, a transceiving flag bit, an equipment address, an endpoint address, a data address and a data length. When an SOF time slot signal arrives, according to the scheme, a queue is polled according to the priority, queue head data is analyzed, and the data transmission direction is determined according to a receiving and transmitting flag bit. Through the mode, the USB host can flexibly communicate with various slave devices, meanwhile, the occupation of endpoint resources is reduced, and the logic complexity and the chip cost of the controller are reduced.

The invention relates to a PDCCH (Physical Downlink Control Channel) adaptive transmission optimization method, which comprises the following steps of: 1, counting SE (Secure Element) and DTX (Discontinuous Transmission), converting reported CQI (Channel Quality Indicator) into the SE, and filtering the SE; step 2, updating the effectiveness of the inner ring according to the SE value and updating the effectiveness of the outer ring according to the PDCCH scheduling times in the given time window obtained by statistics; and step 3, according to the effectiveness of the inner ring and the outer ring and the DTX statistical result, determining different adaptive level adjustment strategies, determining the adaptive level and the like. The method has the advantages that two dimensions of aggregation level and power offset are adjusted as a whole, logic complexity is reduced, implementation is simplified, and expansion is facilitated; according to the invention, both the inner ring and the outer ring maintain the effectiveness, the effectiveness of the inner ring is periodically maintained based on the SE, the self-adaptive level can be flexibly adjusted only according to DTX when the SE is high, and the robustness of PDCCH decoding is improved; the effectiveness of the outer ring is maintained based on DTX, the DTX statistics does not serve as the basis for adjusting the adaptive level when the number of samples in the time window is small, and the accuracy is improved.

The invention relates to a shared bus type distributed MBIST system, and belongs to the technical field of MBIST architecture. According to the shared bus type distributed MBIST architecture, a Memory Interface module in a Tesent MBIST architecture is removed, an MBIST controller is reserved, and a shared bus controller is additionally arranged in the MBIST controller, so that a data path and a control path are built between the MBIST controller and Memory, and the data path and the control path comprise an address bus, a data bus, a read-write enable, a chip selection enable and other control buses which can be reused and are used for accessing the Memory. According to the shared bus type distributed MBIST architecture, a Memory Interface module is not needed, the problems that the chip area and power consumption are large due to the fact that multiple Memory Interfaces need to be adopted at present are solved, logic resources can be reduced to the maximum extent, the logic complexity can be reduced, and testing of Memory in a chip is achieved.

The invention belongs to the field of low-code platform development, and discloses a cross-platform low-code development system and method supporting code export. The method comprises the following steps: dividing a visual layout in a low-code platform into a central process region and R sub-process regions according to a preset rule; obtaining center structure data and sublevel structure data of the target project; obtaining a total logic complexity value of the project based on the central structure data and the sublevel structure data; obtaining an initial flow chart corresponding to the target project; inputting the central structure data, the sub-level structure data, the total logic complexity value and the initial flow chart into a pre-trained flow optimization model to obtain an optimized target flow chart; packaging a target sub-flow in the target flow chart to serve as a reusable plug-in of a cross-project flow; and the running efficiency of the developer project is effectively improved.

The invention provides a PLC control system, and the system comprises a CPU module which executes application logic; the backboard modules are connected in series and are arranged to be communicated with the CPU module and the function modules, and each backboard module can be correspondingly connected with one function module; and the artificial intelligence module is one of the function modules, receives various data, performs data analysis processing on the data processing tasks with the data volume exceeding a preset data volume threshold value or the logic complexity exceeding a preset logic complexity threshold value, and forwards the obtained analysis data to the CPU module through the corresponding backboard module. According to the invention, the edge computing thought is applied to the PLC field, large-scale complex computing is migrated from the CPU module to the artificial intelligence module, the resource consumption of the CPU module is reduced, and the processing performance of the PLC control system is improved on the whole. The large-scale complex calculation is usually easy to generate faults, and the reliability and availability of the CPU module are also improved by independently carrying out the large-scale complex calculation through the artificial intelligence module.

The invention relates to the technical field of chip design, in particular to a cross-cache-line data acquisition method, electronic equipment and a storage medium, and the method comprises the following steps: acquiring a maximum unit total amount M corresponding to a graph drawing command to which a current subtask belongs; reading and splicing data corresponding to continuous (M-1) subunits at the tail of the first cache line address range and data corresponding to continuous (M-1) subunits at the starting end of the second cache line address range to obtain continuous data covering the complete access range of the current subtask, and storing the continuous data in a preset buffer area; the target data is extracted from the buffer area according to the initial address of the current sub-task and the first target number of the first target sub-unit in which the current sub-task falls in the first cache line to which the first target sub-unit belongs, and the target data is used as the input of the distribution operation, so that the logic complexity and the calculation complexity are reduced.

The invention discloses a synchronization method and system based on a state change log, and the method comprises the steps: a main device obtains an alarm state change event, records the state change log, and adds the state change log into a log queue; the slave device initiates a synchronization request to the master device, and the master device judges the consistency of the configuration version based on the synchronization request; if the configuration versions are consistent, the master device performs incremental synchronization condition judgment based on the synchronization request; if yes, the master device sends incremental update data to the slave device; otherwise, the master device sends the total update data to the slave device; the slave device performs incremental synchronization or full synchronization according to the received update data. Under the condition of the existing redundancy deployment master-slave mode, the log of the alarm state change is used as the basis of the alarm state synchronization, and the incremental synchronization and the full-amount synchronization between the master device and the slave device are judged, so that the data transmission pressure caused by frequently adopting the full-amount synchronization is effectively reduced, and the data transmission efficiency is improved. And the logic complexity of data synchronization is reduced.

The invention discloses a data processing method and a related device, and when a to-be-processed task for a target function point is received, if a task queue is empty and the to-be-processed task is matched with a current state, the to-be-processed task is written into the task queue. And if the task queue is not empty and the to-be-processed task is matched with the target state of the target function point after the last task in the task queue is executed, writing the to-be-processed task into the task queue. Finally, the target function point can be called according to the queue sequence to execute the tasks in the task queue, and the queue sequence can be used for indicating the receiving sequence of the tasks in the task queue. Visibly, based on the current state and the condition of the task queue, the to-be-processed tasks which can be correctly executed are screened and written into the task queue, so that the tasks can be correctly executed according to the queue sequence, execution errors are avoided, the queue length is reduced, and the response speed is increased. As the sequence can be adjusted to be a correct sequence, out-of-order calling can be supported, and the logic complexity of a service side is prevented from being increased.

The invention generally belongs to the field of flight simulation, and particularly relates to a HOTAS simulation unit for avionics system simulation. At present, simulation of an aircraft avionics system is mostly that a plurality of independent simulation units are developed for each piece of avionics equipment, but a large number of keys for controlling different equipment under different conditions or executing different functions of the same equipment are involved in control of a modern Hands On Throttle and Stack. Therefore, complex logic interaction and interface design among different avionics simulation units can be involved when the whole avionics system simulation is carried out. According to the software module and the data processing method special for logic processing and function control of the aircraft hand-not-leave-rod system, the current control intention of a pilot is correctly recognized through unified collection and unified judgment of key control information and avionics state information; the method has the advantages of reducing the simulation logic complexity of the avionics system, improving the judgment accuracy, reducing the coupling degree of each avionics simulation unit, shortening the development period and the like.

The invention discloses a scheduling-driven high-level comprehensive array division method, which comprises the following steps of: creating an associated access instruction set for arrays in algorithm design, and analyzing an address calculation expression of each access instruction; on the basis of the control data flow diagram designed by the algorithm, instruction scheduling is executed according to an instruction topological sequence and circuit performance requirements, for an array access instruction, a schedulable interval of the array access instruction is calculated, control steps in the interval are traversed, and incremental address conflicts introduced by each scheduling mode are determined; aiming at each scheduling mode of the array access instruction, a minimum overhead array division scheme capable of solving all address conflicts is searched, and the overhead of the division scheme comprehensively considers the number of storage modules after division, address control logic complexity and time delay; the address conflicts comprise the incremental address conflicts and the stock address conflicts. The method has the advantages that compared with an existing array division scheme, calculation scheduling and array division are organically combined, the cost of array division is reduced, and the scheduling performance is improved.

The application relates to a function module operation method, device and equipment and a storage medium, the method comprising the following steps: a first function module class corresponding to a first function module is created; the first function module class inherits a base class provided by a preset function module development framework; a data service interface for data interaction between modules and an execution interface for executing business logic in a module are arranged in the base class; first output data corresponding to a second function module relied on by the first function module is acquired through the data service interface in the first function module class; the first output data is data provided externally to the second function module through the data service interface in the base class; the execution interface in the first function module class is called, the first function module is operated based on the first output data according to preset business logic. The application reduces the complexity of control logic, reduces resource consumption and improves the decoupling degree between modules through a data driving mode.

The application belongs to the technical field of monotonic counter, and particularly relates to a monotonic counter, a counting method, an electronic device and a storage medium. The counting method of the monotonic counter of the application, under the condition that no abnormal situation occurs, only counts between two storage blocks in turn, and does not need to perform additional storage blocks to back up the storage block counting value under the abnormal situation, thereby optimizing the operation process of counting. Under the condition that an abnormal situation occurs, firstly, whether the external address is the start address of the data bit of the storage block is judged, and then whether the storage block has an abnormality is judged. For the storage block without an abnormality, the counting value is obtained by counting the data bit, so as to ensure accurate counting. For the storage block with an abnormality during counting, the storage block is switched to another storage block for erasing and then switched back to the current storage block for counting. The counting method optimizes the processing steps of counting and abnormal situations, and reduces the logic complexity.

The application relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata and calculating a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model to output an initial adjacency matrix; calling a feedback inhibition mask matrix generated based on a historical operator utility state, performing bitwise logical AND operation on the initial adjacency matrix to generate a corrected effective topological matrix; analyzing the matrix, dynamically indexing a logical operator function pointer in an instruction cache, and constructing a directed acyclic execution linked list; and driving a processor to sequentially call logical operator execution operation, wherein the application determines redundant logic nodes in AI prediction through a bitwise operation mask mechanism based on historical feedback, realizes the deterministic convergence of processing delay and the optimal matching of algorithm resource.

The present disclosure provides a kind of pulse neural network network-on-chip communication method and network-on-chip, the shortest distance between source neuron and target area is propagated in the present disclosure, and global broadcast, cell broadcast and point-to-point propagation are unified, effectively simplify routing algorithm and calculation process, reduce routing logic complexity and network-on-chip delay;And, the data packet forwarding method driven by destination is mainly used, the logic judgment of event data whether receiving data packet is placed in receiving end node, so that the data packet of propagation can be fixed size, the process of finding routing table is saved in transmission process, effectively reduce the storage capacity of routing table, flexibly handle the receiving determination of broadcast communication;At the same time, the uniform field format is used for a variety of types of data packet in the embodiment of the present disclosure, the logic of router processing data packet is simplified, and then the delay generated by data packet through router is reduced.

The invention provides a complexity determination method and device for a flight operation program and a man-machine interaction system, and is applied to the technical field of aviation equipment evaluation. Comprising the steps of performing hierarchical decomposition on a flight operation program corresponding to a flight task to generate a solution sequence of the flight operation program; drawing an action control chart according to the operation action information in the solution sequence; drawing an information interaction diagram according to the attention distribution condition in the solution sequence; drawing a control mode pattern according to the use condition of the control device in the solution sequence; determining operation logic complexity and operation quantity complexity according to a first node in the action control chart; determining information interaction complexity according to a second node in the information interaction graph; the control mode complexity is determined according to a third node in the control mode graph; and determining the first complexity of the flight operation program according to the operation logic complexity, the operation number complexity, the information interaction complexity and the control mode complexity. And the accuracy and continuity of the first complexity are improved.

The embodiment of the invention provides an exception determination method, system and device and a readable storage medium. The method comprises the following steps: aiming at each instruction in a transmitting queue, sequentially sending a speculation pointer request carrying an instruction type to a second controller, and returning a first pointer by the second controller aiming at the speculation pointer request of which the instruction type is a calling instruction; returning a second pointer for the speculation pointer request of which the instruction type is a return instruction; the first pointer and the return address are stored in a first cache, and a second pointer and a return instruction are sent to the branch jump unit; in response to the query request, querying a target first pointer and a target return address corresponding to the target first pointer in a first cache; and returning the target return address to the branch jump unit, comparing the expected return address corresponding to the return instruction with the target return address by the branch jump unit, and determining whether exceptions are generated or not. According to the method, the logic complexity of an instruction submission stage can be reduced.

The invention discloses a method for performing object-oriented programming on a spreadsheet, which is characterized by comprising the following steps of: creating a definition of an object, and storing a definition file in a medium; the definition file of the object contains the definition of one or more objects; the definition file of the object is used for storing the object according to a preset storage format; a method function is created for the object, the method function is used for operating the object, the method function comprises at least one of a first method function, a second method function, a third method function, a fourth method function and a fifth method function, and the first method function is used for reading the object from a definition file to a memory data structure; a second method function to save the object from the memory data structure to a definition file; the third method function is used for returning the object; the fourth method function is used for transforming the input object; and the fifth method function is used for displaying the object in the memory on the interface. According to the method, object-oriented programming is realized on the spreadsheet, and related objects can be operated through the method function, so that the bottom logic complexity is hidden, and the programming efficiency is improved.

The application relates to a default value setting method, device, equipment, medium and program product of a nuclear power plant. The application relates to the technical field of nuclear power. The method comprises the following steps: acquiring an input signal of a function block in a digital control system of a nuclear power plant; determining a quality bit of the input signal according to a preset interval range and a numerical value in the input signal; and delivering the quality bit to other function blocks connected with the function block. The method can avoid increasing the logic complexity.

The embodiment of the present application provides a computing circuit and an artificial intelligence accelerator, which relate to the field of integrated circuit technology. The computing circuit receives multiple first blocks of floating-point numbers, calculates the multiple first blocks of floating-point numbers, and obtains multiple second blocks of floating-point numbers, which includes: a first computing unit, a conversion unit, and a second computing unit; the first computing unit receives multiple first blocks of floating-point numbers, calculates the mantissa items of the multiple first blocks of floating-point numbers, and obtains multiple first intermediate floating-point numbers; the conversion unit normalizes the multiple first intermediate floating-point numbers into multiple normalized mantissa items; the second computing unit calculates the multiple normalized mantissa items to obtain multiple second intermediate floating-point numbers, and normalizes the multiple second intermediate floating-point numbers into multiple second blocks of floating-point numbers based on the normalized mantissa items. The computing circuit reduces the logic complexity and power consumption of the circuit, effectively reduces the data storage requirements, and solves the problem of insufficient storage space and bandwidth for artificial intelligence services.

The invention relates to the technical field of risk control, in particular to a rule engine construction method and system based on multi-dimensional rule fusion. The method comprises the following steps: in response to a risk control request, querying user information based on a user identifier obtained from the risk control request; in response to the query request, querying a rule execution chain based on a province code and a product code obtained from the risk control request; the rule execution chain comprises a plurality of first rules of different rule types sorted based on rule weights; in response to the rule execution request, executing a rule execution chain to obtain an execution link record at least comprising a verification state, the verification state representing whether the user passes verification; and responding to the execution of the rule execution chain, packaging the verification state to the network response, returning the network response to the user terminal, and classifying the first rule according to the executed function, so that the rules of different rule types are mutually independent during execution, the execution logic complexity of the rules is reduced, and the execution efficiency of the first rule is improved.

The present application relates to the technical field of chip design, in particular to a cross cache line data acquisition method, electronic equipment and storage medium, which obtains the maximum unit total amount M corresponding to the current subtask belonging to the graphics rendering command; reads and splices the data corresponding to the (M-1) subunits continuous at the end of the first cache line address range and the data corresponding to the (M-1) subunits continuous at the beginning of the second cache line address range, obtains the continuous data covering the complete access range of the current subtask and stores it in the preset buffer; according to the starting address of the current subtask and the first target number of the first target subunit falling in the first cache line, the target data is extracted from the buffer, and the target data is used as the input of the distribution operation, which reduces the logical complexity and the calculation complexity.

This utility model discloses a multi-system, multi-channel digital TR synchronization circuit, comprising a GPS / BD timing module, a system clock source, a multi-channel digital TR board, and a system lead generation device. The rubidium clock and second pulse of the GPS / BD timing module are respectively connected to the system clock source and the lead generation device. The sampling clock and lead clock of the system clock source, and the lead signal of the system lead generation device are respectively connected to each multi-channel digital TR board. The system lead clock of the system clock source is also connected to the lead generation device. This scheme uses the rubidium clock and second pulse of the GPS / BD timing module as a reference, and the accuracy of the lead clock determines the synchronization accuracy (e.g., a 20MHz lead clock synchronization error ≤50ns). Multi-system expansion can be achieved by adding timing modules without refactoring the hardware architecture. Its hardware and software integration reduces FPGA logic complexity, reduces hardware costs by relying on chip synchronization functions and equal-length wiring design, and ensures multi-channel synchronization stability through same-source clock allocation and equal-length signal design.

The present invention is applicable to the field of processor technologies, and particularly relates to a management method, apparatus, and storage medium for a register file cache. The management method includes the following steps: obtaining an instruction to be executed through the processor front end for branch prediction processing and decoding processing, and sending the processed instruction to be executed to the processor back end; performing an operation on the instruction to be executed by the processor back end to obtain an operation result, and writing the operation result back to the register file module according to the storage state of the register file module of the processor back end and the cache management policy. Compared with the prior art, the present invention reduces the hardware overhead, logical complexity, and dynamic power consumption, and reduces the complexity brought by cache coherence maintenance operations under the condition of ensuring that the number of read / write ports of the register file module meets the requirements through the cache management policy and the corresponding processing mechanism during pipeline flushing. When pipeline flushing occurs, no time and hardware resources are spent flushing the cache.

The embodiment of the invention relates to the field of integrated circuits, and discloses a floating-point number addition and subtraction device and method. In the invention, the negation processing is carried out on the smaller mantissa through a negation control signal control mechanism, so that the whole device only needs to execute the negation operation once or does not need to execute the negation operation, multiple times of conversion between an original code and a complement code is avoided, the logic complexity and hardware resource occupation are remarkably reduced, and the overall operation speed is improved. Meanwhile, based on a negation control signal mechanism, the output result of the mantissa operation module is always a positive number, so that the leading zero / one counter is simplified into a leading zero counter, and the number and complexity of circuit logic modules are further reduced. In addition, the transmission gate control sub-module and the transmission gate array sub-module are used for carrying out normalization shift on mantissa, and compared with a traditional multi-level multi-selection selector scheme, the shift path is effectively shortened, delay caused by large-scale gate level cascading is reduced, and the circuit calculation performance is improved.

The present application provides a method, device and human-computer interaction system for determining the complexity of a flight operation procedure, which are applied to the technical field of aviation equipment evaluation. The method includes: hierarchically decomposing the flight operation procedure corresponding to a flight mission to generate a solution sequence of the flight operation procedure; drawing an action control diagram according to the operation action information in the solution sequence; drawing an information interaction diagram according to the attention allocation situation in the solution sequence; and drawing a control mode diagram according to the usage situation of control devices in the solution sequence; determining the operation logic complexity and the operation quantity complexity according to the first nodes in the action control diagram; determining the information interaction complexity according to the second nodes in the information interaction diagram; and determining the control mode complexity according to the third nodes in the control mode diagram; determining a first complexity of the flight operation procedure according to the operation logic complexity, the operation quantity complexity, the information interaction complexity and the control mode complexity. The accuracy and continuity of the first complexity are improved.

Provided in the present application is a PLC control system, comprising: a CPU module for executing application logic; a plurality of backplane modules connected in series and configured to connect the CPU module to functional modules, wherein each backplane module can be correspondingly connected to one functional module; and an artificial intelligence module, which is one of the functional modules, receives various data, performs data analysis processing on a data processing task of which the data volume exceeds a preset data volume threshold or the logic complexity exceeds a preset logic complexity threshold, and forwards obtained analysis data to the CPU module by means of the corresponding backplane module. The present application applies the edge computing concept to the field of PLCs, and migrates large-scale complex computing from the CPU module to the artificial intelligence module, thereby reducing the resource consumption of the CPU module, and improving the overall processing performance of the PLC control system. Large-scale complex computing is also usually prone to failure, such that individually performing large-scale complex computing by means of the artificial intelligence module also improves the reliability and availability of the CPU module.

The invention discloses a software complexity balanced distribution system and method.The system comprises an input module, a state machine and an output module which are in communication connection, and the system distributes the logic complexity of software in the input module, the state machine and the output module in a balanced mode based on data flow and control flow; the input module is used for processing an input signal; the state machine is used for executing state jump or controlling output according to current data and events; and the output module is used for performing output processing on the signal. According to the invention, the logic complexity of the software is distributed to the input module, the state machine and the output module in a balanced manner, so that the logic complexity of the input module, the state machine and the output module is balanced; the logic decoupling work and the adaptive workload of the input module, the state machine and the output module are reduced, and the universality of the input module, the state machine and the output module is improved.