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Delta-sigma modulator based on digital-noise coupling technology

A digital noise and modulator technology, applied in the field of delta-sigma modulators, can solve problems such as logic delay and exponential increase in hardware complexity

Active Publication Date: 2014-07-16
UNIV OF SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is: for the delta-sigma modulator using a high-precision quantizer, while solving the problem of exponential growth of its hardware complexity, avoid the logic delay problem existing in the existing solution

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  • Delta-sigma modulator based on digital-noise coupling technology
  • Delta-sigma modulator based on digital-noise coupling technology
  • Delta-sigma modulator based on digital-noise coupling technology

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Embodiment Construction

[0049] The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0050] The specific embodiments of the present invention are set forth below, because the basic inventive concept of the present invention is as follows: figure 2 , 3 As shown, the noise shaping is realized by coupling the LSB part of the output of the quantizer to the input of the quantizer, and the noise is in digital form. Therefore, we refer to the modulator of the present invention as a Δ based on digital noise coupling technology. -Σ (delta-sigma) modulator. The modulator is introduced below.

[0051] The structure diagram of the delta-sigma (delta-sigma) modulator based on digital noise coupling technology is as follows: Figure 4 As shown, it mainly includes analog subtracter 1, analog filter 2, analog adder 3, quantizer 4, delay unit 5, auxiliary digital-to-analog converter (DAC2) 6, dynamic element matching unit (DEM)...

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Abstract

The invention discloses a delta-sigma modulator based on the digital-noise coupling technology. The structure of a traditional noise coupling delta-sigma modulator is improved, and the output of a quantizer is divided into an MSB part and an LSB part. The MSB part is directly fed back to the input end of the modulator; the LSB part is fed back to the input of the quantizer after digital-to-analogue conversion; then the MSB part and the LSB part are recombined after digital post-processing. The digital-noise coupling technology can fully represent the performance advantage of the high-precision quantizer, the problem of the exponential growth of the matching logic complexity of dynamic components is avoided, the logic time delay of introduction of a digital delta-sigma remodulation scheme provided by formers is also avoided, the quantizing noise leakage caused by mismachining between analog and digital noise transfer functions is further restrained, and therefore the requirement for design of an operational amplifier is lowered, implementation is easy, and the modulator is very suitable for low-power dissipation and broadband application.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a delta-sigma modulator based on digital noise coupling technology. Background technique [0002] The delta-sigma modulator is a typical high-precision analog-to-digital converter structure widely used in communication systems. Moreover, in order to reduce power consumption and prolong the standby time of communication systems, the demand for low-power delta-sigma modulators is increasing. Among various circuit design techniques to reduce the power consumption of delta-sigma modulators, the most direct one is to increase the number of bits of the quantizer, which reduces the quantization noise, thereby reducing the design requirements of the integrator, so it is especially suitable for power supply It is used under the advanced CMOS process after voltage reduction. However, increasing the quantization accuracy of a traditional Flash quantizer will expone...

Claims

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Application Information

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IPC IPC(8): H03M3/00
Inventor 贺林张云程龙芳林福江
Owner UNIV OF SCI & TECH OF CHINA
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