Memory cell structure of SRAM

Abstract

The invention discloses a memory cell structure of an SRAM (static random access memory), a main body structure consists of two NMOS (N-channel Metal Oxide Semiconductor) tubes and six PMOS (p-channelmetal oxide semiconductor) tubes, and the two transmission tubes are both PMOS (p-channel metal oxide semiconductor) tubes. The drain electrodes of the first NMOS tube and the second PMOS tube and the grid electrodes of the fifth PMOS tube and the second NMOS tube are connected with a Q node; the drain electrodes of the second NMOS tube and the third PMOS tube and the grid electrodes of the sixthPMOS tube and the first NMOS tube are connected with a QN node; the drain electrode of the first PMOS tube, the source electrode of the fifth PMOS tube, the grid electrode of the third PMOS tube andthe grid electrode of the fourth PMOS tube are all connected with a third node; the drain electrode of the fourth PMOS transistor, the source electrode of the sixth PMOS transistor and the grid electrodes of the first PMOS transistor and the second PMOS transistor are all connected with a fourth node; the source electrodes of the first to fourth PMOS tubes are connected to a power supply voltage,and the source electrodes of the first NMOS tube and the second NMOS tube and drain electrodes of the fifth PMOS tube and the sixth PMOS tube are grounded. The soft error resistance and the read static noise tolerance of the circuit can be improved, and the electric leakage power consumption can be reduced.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a storage unit structure of a static random access memory (SRAM). Background technique [0002] The advancement of integrated circuit technology nodes has brought many challenges to the reliability of chips, one of which is soft errors caused by single event upset (SEU) caused by single event effects. [0003] Soft errors can occur in different electronic devices such as automotive electronics, medical devices, etc. [0004] In recent years, due to the continuous advancement of process nodes, devices are getting closer and smaller, which makes single event upset an important source of soft errors. [0005] The memory cell structure of the existing SRAM usually adopts a 6-tube structure. This 6-tube memory cell itself has a poor ability to resist soft errors, so it is necessary to add an anti-soft error cell, so the leakage power consumption of the 6-tube memory cell and the ...

AI Technical Summary

Problems solved by technology

Depend on figure 1 It can be seen that when any one of the Q node and QN node is disturbed, it is easy to flip, and this structure does not have the ability to resist soft errors

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