Low power consumption design method for SRAM (static random-access memory) type FPGA (field-programmable gate array)

Abstract

The invention provides a low power consumption design method for a SRAM (static random-access memory) type FPGA (field-programmable gate array), which includes steps: firstly, building a leakage power information graph according to structure and circuit information of the FPGA; secondly, evaluating leakage power of each MUX during wiring phase to obtain the leakage power; thirdly, importing the leakage power to wiring cost function to lower circuit leakage power. By implementing low power consumption design during the wiring phase and comprehensively considering delay consumption, congestion consumption and leakage power consumption of the circuit during the wiring process, timing performance of the circuit is hardly affected. By modifying circuit wiring manner to implement low power consumption design, the method is irrelevant with chip structure of the FPGA and suitable for current mainstream FPGA, processing of the FPGA chips is not affected and no extra area consumption is imported.

Description

technical field [0001] The present invention relates to the technical field of low power consumption design of FPGA (Field Programmable Logic Gate Array) circuit, particularly, the present invention relates to a kind of low power consumption design method of SRAM (static random memory unit) type FPGA widely used at present. Background technique [0002] For a long time, FPGA circuit has been widely concerned by circuit designers because of its short design cycle and low development cost. With the continuous improvement of chip performance, circuit design based on SRAM FPGA is widely used in communication engineering, industrial control, embedded development and other fields. However, due to the reduction of transistor feature size and the continuous reduction of threshold voltage, the leakage power consumption of SRAM FPGA increases rapidly, which has become a bottleneck restricting the further application of SRAM FPGA. The power consumption not only directly affects the pa...

AI Technical Summary

Problems solved by technology

[0008] 1. The timing has a great influence

Type (1) low-power design method to configure the circuit power supply voltage and transistor threshold voltage will affect the switching characteristics of the transistor, thereby affecting the timing performance of the circuit

[0009] 2. The scope of application is limited

The low-power design method of category (1) is optimized from the perspective of FPGA chip structure, which will have an impact on the process of FPGA chip manufacturing, and is not applicable to existing FPGA chips.

[0010] 3. There is additional area overhead

The low-power design method of type (2) only considers the relationship between the output logic value of the MUX structure and the average leakage power consumption, and does not further consider the relationship between the leakage power consumption in the MUX structure and the access logic and bypass logic. Limited headroom for power optimization

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