8 results about "Wilson current mirror" patented technology

A voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator comprising: a voltage supply terminal for receiving a supply voltage; an output terminal for outputting the regulated output voltage; a reference terminal; a feedforward Wilson current mirror comprising: a Wilson current mirror with an input current terminal and an output current terminal; an input current source coupled between the supply voltage terminal and the input current terminal of the Wilson current mirror; a feedforward capacitor arranged in parallel with the input current source; and an output current transistor with a conduction channel coupled between the supply voltage terminal and the output current terminal of the Wilson current mirror; and a flipped voltage follower, FVF, comprising: a pass transistor comprising a conduction channel coupled between the supply voltage terminal and the output terminal; a first FVF transistor with a conduction channel coupled between the output voltage and a FVF node; a second FVF transistor with a conduction channel coupled between a gate of the pass transistor and the FVF node; a third FVF transistor with a conduction channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein a gate of the third FVF transistor is coupled to a gate of the output current transistor; and a FVF current source coupled between the FVF node and the reference terminal.

To provide an envelope tracking system in which changes in power amplifier supply voltage arising from envelope tracking are compensated.SOLUTION: An envelope tracking system includes a power amplifier 250 that receives power from a power amplifier supply voltage VPA and amplifies a radio frequency (RF) signal RFIN. The power amplifier includes: an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal; a Wilson current minor 232; and a field-effect transistor NFET 231 for amplifying the RF signal. The Wilson current mirror includes: an input that receives a reference current IREF from a reference current source 236; and an output connected to the power amplifier supply voltage. The NFET amplifies an RF input signal to generate an RF output signal RFOUT. Additionally, a gate of the NFET is biased by an internal voltage of the Wilson current mirror and a source receives a ground voltage, while a drain receives the power amplifier supply voltage from a choke inductor 235.SELECTED DRAWING: Figure 3

A voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator comprising: a voltage supply terminal for receiving a supply voltage; an output terminal for outputting the regulated output voltage; a reference terminal; a feedforward Wilson current mirror comprising: a Wilson current mirror with an input current terminal and an output current terminal; an input current source coupled between the supply voltage terminal and the input current terminal of the Wilson current mirror; a feedforward capacitor arranged in parallel with the input current source; and an output current transistor with a conduction channel coupled between the supply voltage terminal and the output current terminal of the Wilson current mirror; and a flipped voltage follower, FVF, comprising: a pass transistor comprising a conduction channel coupled between the supply voltage terminal and the output terminal; a first FVF transistor with a conduction channel coupled between the output voltage and a FVF node; a second FVF transistor with a conduction channel coupled between a gate of the pass transistor and the FVF node; a third FVF transistor with a conduction channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein a gate of the third FVF transistor is coupled to a gate of the output current transistor; and a FVF current source coupled between the FVF node and the reference terminal.

A system and method for autonomous machine identity succession utilize a hardware-rooted semantic sentinel and an analog neuromorphic audit engine to ensure state integrity. The system detects micro-architectural threat signatures through continuous asynchronous voltage monitoring and gates cryptographic signatures via a low-impedance analog interlock circuit physically interposed on a processor signature-enable line. Behavioral integrity is verified through an adversarial “Proof of Logical Alignment” handshake, where proposed action vectors are audited via an analog memristor crossbar array utilizing physical current summation replicated through a high-impedance Wilson Current Mirror isolation barrier. The invention ensures the atomic migration of identities across heterogeneous hardware architectures through a “Handshake-and-Zeroize” protocol, utilizing a series-pass isolation switch and crowbar MOSFET circuit to provide irreversible thermodynamic destruction of the source state.

A voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator comprising: a voltage source terminal; an output terminal; a reference end; a feed-forward Wilson current mirror; an input current source; a feed-forward capacitor; and an output current transistor; and a flip voltage follower (FVF) including: a channel transistor including a conductive channel coupled between a supply voltage terminal and an output terminal; a first FVF transistor having a conductive channel coupled between the output voltage and the FVF node; a second FVF transistor having a conductive channel coupled between the gate of the channel transistor and the FVF node; a third FVF transistor having a conductive channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein the gate of the third FVF transistor is coupled to the gate of the output current transistor; and an FVF current source coupled between the FVF node and a reference terminal.

The application belongs to the technical field of power electronics, and provides an active gate drive circuit based on variable resistance and variable current regulation, which comprises a control unit, an isolated gate drive module, a gate variable resistance module, a gate variable current module, a power loop and a gate voltage feedback module. The application combines discrete resistance switching (coarse adjustment) with linear current source regulation (fine adjustment), realizes fine management of the switching trajectory of a power device, limits the current variation rate by initially connecting a large resistance in the on process, then switches to a low resistance to accelerate conduction, and splits part of the current from the gate through a Wilson current mirror structure to suppress current overshoot, and in the off process, initially discharges rapidly through a low resistance, then switches to a high resistance to increase damping, and injects a compensation current into the gate through a current mirror to suppress voltage ringing.

A level shifter includes a Wilson current mirror circuit outputting an output voltage of an output node based on a first input voltage inverting a phase of an input voltage and a second input voltage inverting the phase of the first input voltage, a leakage current control circuit receiving the output voltage and controlling a leakage current generated in the Wilson current mirror circuit using the output voltage, and a latch circuit providing a voltage of a logic high level to the output node when the output voltage is a logic high level.

To reduce and suppress influence of an error of a base current of a NPN type bipolar transistor to provide a more accurate output current of a square circuit used in an analog circuit in an integrated circuit.SOLUTION: A square circuit according to the present invention has a first current mirror circuit 51 input with an input current IIN, and a Wilson current mirror circuit 52 formed at the succeeding stage. The first current mirror circuit 51 has first and third bipolar transistors 1, 3 current-mirror connected to each other. A gate of a first MOS transistor 11 is connected to a collector of the first bipolar transistor 1, and a source of the first MOS transistor 11 is connected to bases of the first and third bipolar transistors 1, 3. The Wilson current mirror circuit 52 is formed of second to fourth MOS transistors 12 to 14, which reduces and suppresses influence of a base current error. Thus, a high-accuracy square output current is obtained at a collector of a fourth bipolar transistor 4.SELECTED DRAWING: Figure 1