Low-power design optimization method for instruction-level parallel processor

Abstract

The invention relates to a low-power design optimization method for an instruction-level parallel (ILP) processor. The method comprises the steps of analyzing a hardware resource and parallelism demand information of each part of an input application program by utilizing a compiler, and obtaining basic blocks of the application program as well as a control flow graph (CFG) and loop hierarchy trees (LHTs), which are formed by the basic blocks; identifying regional cores; expanding a region, combining the residual basic blocks in the region, finding out the regional cores directly connected with the residual basic blocks, comparing executive frequencies of edges connecting the regional cores, finding out the edge with the maximum executive frequency, and combining the basic block connected with the maximum edge in the regional cores until the residual basic blocks do not exist; and re-scheduling the application program, scheduling each region by using the set parallelism, inserting a power gating instruction before executing each region, and turning off idle hardware resources to reduce electric leakage power consumption. According to the method, the influence of the electric leakage power consumption on the working performance of the processor can be reduced and the utilization rate of the hardware resources in the ILP processor can be increased.

Description

Technical field [0001] The invention belongs to the technical field of computer architecture design and relates to a low power consumption design optimization method. Background technique [0002] In recent years, electronic products such as smart phones and wearable smart devices have developed rapidly. Almost everyone owns an electronic device. The execution speed of these electronic devices can meet the needs of most users, but the problem of power consumption is particularly prominent. It often affects the performance and operation time of the equipment; especially in the Internet + era, the performance requirements for computers and smart phones are getting higher and higher, and the energy efficiency of the equipment is improved, that is, reducing power consumption is the key to reducing the power consumption without affecting the execution speed of the equipment. more and more important. [0003] The main reason for the fast execution speed of these electronic device...

AI Technical Summary

Problems solved by technology

The huge challenge in the application of power gating technology is that in the process of switching the circuit state, it will generate a lot of energy consumption and delay, which makes the circuit cannot be turned on and off at any time, and the power gating command must be inserted to the right place

However, the AFReP algorithm proposed by Tabkhi in 2014 did not consider the additional energy consumption of the state transition generated by the power gating technology, but only inserted the power gating command before executing each function in the application program, which caused the hardware device to be turned on frequently, that is, every time a The function changes the hardware configuration once, and the frequent opening of the hardware device results in a large amount of extra energy consumption. The overall evaluation of the energy-saving effect of AFReP shows that although the leakage energy consumption is reduced, a large amount of extra energy consumption is generated, and the effect is not good.

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